I'm using a 28335 McBSP channel to extract data from an ADC that is "SPI compatible." Unfortunately, the ADC supplies its own data ready signal that is brilliantly synchronized to the sample clock, not the SCLK input. This means I am forced to supply SCLK (from MCLKRB, to be precise) while receiving a frame synchronization signal on MFSRB. Since the frame synchronization signal is not synchronized to the SCLK provided by the DSP, reliable reception is all but impossible. I've tried using clock stop mode to no avail. In clock stop mode it appears that either both the clock and frame synchronization are inputs (SPI slave) or outputs (SPI master), though this is only implied in the McBSP documentation in the SPI mode section.
What I need to do is force my output clock to synchronize to the incoming frame synchronization signal. Based on the description of clock stop mode, it seems like this should be possible but I simply cannot get it to work. Any suggestions?
Thanks,
Mark Takatz