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CW/CCW Support on the C2000 eQEP Module

Other Parts Discussed in Thread: CONTROLSUITE

Hi C2000 Champion

Customer want to apply CW/CCW in F2833x, and read the application note:CW/CCW Support on the C2000 eQEP Module.

Customer want the reference circuit and the test source code, could you provide these?

Eric

  • Hi Eric,

    The application report provides a good summary of what was done and has some of the information you are asking for embedded in it. 

    Please note that the report was largely targeted to providing a proof-of-concept to the customer.  It is not a full TI Design.

    The verification section of the report highlights the main method we used to prove whether the interface was working correctly or not.    We felt this was adequate for a proof-of-concept design.  A few other minor tests were done initially, but we did not note them down in the applications report.

    The circuitry that we used is contained in the report.  Note that there are likely improvements that could be made to increase robustness.

    The lines of code in the report could be added to one of the controlSUITE eQEP examples to create a working project.


    Thank you,
    Brett

  • Hi Brett

    Do you have the below SCH record for us? just for convenience customer test.

    Another question is, whether have any special requirement of logic DIPs, can customer change to CD74HC series?

    Thank you!

  • Hi Eric,

    We implemented the circuitry on a breadboard and never built an official schematic for it. 
    (we did have something written in pencil that we worked with, but I was unable to find it in this project's repository.  The figure in the App Report will tell most of the story though)

    Because the circuit was built on a breadboard, using DIP packages was helpful.  CD74HC should be an adequate replacement.  Please make sure it is powered with 3.3V though (so it can interface directly with the C2000). 

    Depending on the max speed specification of the PLC's PTO outputs, it may become necessary to use a logic chip instead of resistive dividers.

    For the most part the interface is relatively straightforward.  The only major thing to watch out for is described in section 3.4 ("Timing Issues").  Some planning may be necessary to ensure that the DIR path is a bit faster than the CLK path.  This could be enforced via the external logic or the C2000 GPIO input qualification could be used to delay the CLK path a few cycles.

    Hopefully this helps!


    Thank you,
    Brett

  • Hi Brett
    Your comments are very help!
    Thank you!

    Eric