Hello,
I'm implementing a UART communication protocol to an F28027F & InstaSpin based customer project. The customer protocol format require 2400Baud via 7-bit data length and use even parity with 1bit stop.
By manually breakpoint check before the data was sent into SCITXBUF, I can ensure SCICCR and other registers are configured correctly. But by debugging, the oscilloscope waveforms had shown that whether I select to use odd or even parity, the SCI port can only sendout parity bit as odd parity configuration.
Also, before checking the TX I was debugging RX path from customer device. The received waveform from oscilloscope check is correct for 7-bit data length and even parity configuration, but whether I select to use odd or even parity bit to receive, the SCIRXST will only give Parity Error Flag and reject to receive. At the beginning I thought it maybe caused from customer device clock jitter or rising edge delay from optical coupler as isolation, but since the TX path sent waveform by F28027F have the similar parity issue (which use internal 10MHz osc as main clock source), I'm not sure where I can check to locate the problem.
Does anyone have some suggestions? Thanks.
Best Regards.
Harvey Wang
