TMS320F28375D reconfiguration after booting CPU2

Hi,

Is any reconfiguration of pins, registers, etc required after booting CPU2 from CPU1?

I have an application that resides in an EEPROM and I set the DCSM OTP BOOTCTRL register in CPU1 to boot from it from SPI.

CPU1 boots from the EEPROM then sends an IPC command to boot CPU2 from the same EEPROM and the application knows which CPU it's running on and behaves differently.

Right now, the CPU2 part just blinks an LED while the CPU1 part allows downloading a new image into the EEPROM.

The issue I am having is that CPU1 cannot access the EEPROM after CPU2 has booted. The SPI pins aren't wiggling like they should, which leads me to believe that I need to reconfigure them, which I have tried unsuccessfully to do.

The SPI accesses work when just running the CPU1 part, so the problem only occurs when CPU2 is running.

Here's the related code:

  //SPI-A connected to CPU02
  DevCfgRegs.CPUSEL6.bit.SPI_A = 1;
  //Allows CPU02 bootrom to take control of clock configuration registers
  ClkCfgRegs.CLKSEM.all = 0xA5A50000;

  // configure GPIO SPI pins for CPU2
  blGpioSetupPinOptions(EE_SPI_SIMO_PIN, GPIO_OUTPUT, GPIO_PUSHPULL);
  blGpioSetupPinMux(EE_SPI_SIMO_PIN, GPIO_MUX_CPU2, GPIO58_SPISIMOA);

  blGpioSetupPinOptions(EE_SPI_SOMI_PIN, GPIO_INPUT, GPIO_ASYNC);
  blGpioSetupPinMux(EE_SPI_SOMI_PIN, GPIO_MUX_CPU2, GPIO59_SPISOMIA);

  blGpioSetupPinOptions(EE_SPI_CLK_PIN, GPIO_OUTPUT, GPIO_PUSHPULL);
  blGpioSetupPinMux(EE_SPI_CLK_PIN, GPIO_MUX_CPU2, GPIO60_SPICLKA);

  GpioDataRegs.GPBDAT.bit.AFE_EE_SPI_CSn_BIT = 1; // default to high
  blGpioSetupPinOptions(EE_SPI_CSn_PIN, GPIO_OUTPUT, GPIO_PUSHPULL);
  blGpioSetupPinMux(EE_SPI_CSn_PIN, GPIO_MUX_CPU2, GPIO61_GPIO);

  //CPU01 to CPU02 IPC Boot Mode Register (SPI)
  IpcRegs.IPCBOOTMODE = 0x4;
  // CPU01 To CPU02 IPC Command Register
  IpcRegs.IPCSENDCOM  = 19;
  // CPU01 to CPU02 IPC flag register
  IpcRegs.IPCSET.all = 0x80000001;

  //SPI-A connected to CPU01
  DevCfgRegs.CPUSEL6.bit.SPI_A = 0;
  //Allows CPU01 to take control of clock configuration registers
  ClkCfgRegs.CLKSEM.all = 0xA5A50002;

  // Set GPIO SPI pins back to CPU1
  blGpioSetupPinOptions(AFE_EE_SPI_SIMO_PIN, GPIO_OUTPUT, GPIO_PUSHPULL);
  blGpioSetupPinMux(AFE_EE_SPI_SIMO_PIN, GPIO_MUX_CPU1, GPIO58_SPISIMOA);

  blGpioSetupPinOptions(AFE_EE_SPI_SOMI_PIN, GPIO_INPUT, GPIO_ASYNC);
  blGpioSetupPinMux(AFE_EE_SPI_SOMI_PIN, GPIO_MUX_CPU1, GPIO59_SPISOMIA);

  blGpioSetupPinOptions(AFE_EE_SPI_CLK_PIN, GPIO_OUTPUT, GPIO_PUSHPULL);
  blGpioSetupPinMux(AFE_EE_SPI_CLK_PIN, GPIO_MUX_CPU1, GPIO60_SPICLKA);

  GpioDataRegs.GPBDAT.bit.AFE_EE_SPI_CSn_BIT = 1; // default to high
  blGpioSetupPinOptions(AFE_EE_SPI_CSn_PIN, GPIO_OUTPUT, GPIO_PUSHPULL);
  blGpioSetupPinMux(AFE_EE_SPI_CSn_PIN, GPIO_MUX_CPU1, GPIO61_GPIO);

Is there anything i'm doing wrong or need to do in addition to this?