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F28335 + ENC28J60

kalpesh Ramani
Prodigy 100 points


Hi,

I am interfacing F28335 chip to ENC28J60(Ethernet chip).

I had developed code for this interface and working fine as it should be. I had set static IP to DSP and i can ping it from PC. (Both are connected directly)

But problem is,

To make all this working, I need to connect one dummy CRO probe to CLK pin and ground to DSP. (Other side jack of CRO probe is not connected any where, it is floating)

If i remove that probe then system stops to work. 

Anyone have idea, what is going on at 1st look?

 

NOTE : There below listed pins are connected to ENC chip from F28335 DSP.

MOSI, MISO, CLK, CS, VCC 5V, GND

 

Thanks,

kalpesh

  • 0
    TI__Guru* 95315 points

    Kalpesh,

     The probe capacitance has the effect of increasing rise/fall time on the CLK signal. You may see the same effect with a 10pF capacitor on the CLK signal. My suspicion is that your SPI timings are marginal. Some timing requirement is right on the edge..

  • 0 in reply to Hareesh Janakiraman
    Prodigy 100 points

    Hi Hareesh ,

    I look into it and find that DSP is generating wrong signal.

    I set SPI to MODE 0 (POLARITY = 0, PHASE = 0). So signal on DATA line ( MOSI, MISO) should change on positive cycle but they are changing according to SPI MODE 1(On Negative cycle).

    Check attachment.

    Thanks,

    Kalpesh.

  • 0 in reply to kalpesh Ramani
    TI__Guru* 95315 points
    Kalpesh,
    Please attach the scope waveforms that clearly illustrate this behavior. Ensure the image shows all 4 SPI signals clearly (in the same order shown in the User guide). Also attach the image of the SPICCR & SPICTL registers from CCS watchwindow.
  • 0 in reply to Hareesh Janakiraman
    Prodigy 100 points

    Ok Hareesh sure i will, But i think we need to wait for that because i just stuck at board security.

    Once i was loading code in FLASH and power gone, thus board locked. I am recovering it, once it done then i will post waveform with register details.

    Thanks,

    Kalpesh.

  • 0 in reply to kalpesh Ramani
    TI__Guru* 95315 points

    Just FYI, the 4th bullet below in our docs is incorrect. We are progressively correcting it in our docs as we revise them: currently, our docs say "falling" instead of "rising"

     

    Four clocking schemes (controlled by clock polarity and clock phase bits) include:

    – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

    – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

    – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

    – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

     

  • 0 in reply to Hareesh Janakiraman
    Prodigy 100 points

    Hi Hareesh,

    After unlocking of DSP, I have tried to regenerate the problem(SPI MODE) but it didn't regenerate.

    But still i am surprise like, ENC28J60 works only in MODE0 and in our case we need to set MODE1.

    Anyway,

    For now i request you to close this post.

    Thanks,

    Kalpesh