F28069 PLL disable: slow access with UniFlash when erasing the Flash

Mathieu,

What is the external clock frequency? Are clocking through X1 pin?

Regards,
Manoj

Mathieu,

Uniflash needs to know your SYSCLK frequency. How are you providing that input to uniflash?

When you bypass PLL, you have to enter PLLCR = 0x0000. Flash API algorithm timings are calculated as if you are trying to run the API @ 5MHz. Hence, the whole algorithm execution would become slow.

Regards,
Manoj

Thanks Manoj.

I have CCS UniFlash Version: 3.4.1.00012 and in the User Interface the "Clock Configuration" settings are set automatically and cannot be modified:

OSCCLK: 10Mhz -> I guess set to this value to use the internal oscillator

CLKINDIV=2

PLLCR= 18

So I guess UniFlash connects to the target and set these settings in the target. So I do not understand why the settings of the current application loaded in the device impact the Flash operation.

Am I wrong?

How did you manage to bypass PLL when the clock configuration settings cannot be modified?

Regards,

Manoj

Hi Manoj,

Sorry I am not clear.

I have my own application that disables the PLL because our external clock is 24Mhz and that we want 24Mhz as SYSCLKOUT and reduce the power consumption as much as possible.

When I have this application in my board (same thing on the F28069M Launchpad) and try to flash another application with Uniflash the Flash bank erasing is very very slow.

When I have the same application (except that PLL is enable), in this case the flash erasing is done faster that in the previous case.

Is it more clear?

Are you interesting to do the test ? I may prepare to you my application that is then very slow to erase flash.

Regards,

Mathieu

Mathieu,

I believe the trick is to make sure PLL isn't disabled when uniflash is programming flash.

I believe you should have set your boot mode pins set to boot to flash. On board powerup / reset, your initial application code disable PLL and when you try to reprogram flash using uniflash, it runs at 5 MHz and hence flash gets programmed at much slower frequency. Hence the very slow flash erase time.

Did you already try settings boot mode pins to boot to sci and then try to re-flash using UNIFLASH. This make sure your application code doesn't disable the PLL before uniflash starts programming.

Regards,
Manoj

Hi,

Thanks a lot for your feedback.

In CCS Uniflash  Version: 3.4.1.00012 with the session (TMS320F28069, Spectrum Digital XDS510USB), when we want to flash the following

settings are hardcoded in the GUI of UniFlash:

OSCCLK = 10Mhz, CLKINDIV = 2, PLLCR = 18

With this setting the flash operation will be done at 90 Mhz (10Mhz *18/2).

What you indicated is that in my case as the board is calling my application at boot time and because my application disables the PLL, the Flash operation is done at 10Mhz/2 ie 18 times slower that expected.

Am I wrong?

So it means that the values used during the flashing are not the one indicated in the GUI Uniflash ?

I am a little bit surprised because I would imagine that the program loaded by Uniflash to flash the code will first set some settings such as the PLLCR and DIV..

Thanks for your support

Mathieu

Mathieu,

I believe that is what is happening. Did you already try setting boot mode pins to SCI boot? This experiment will confirm this.

Regards,
Manoj

Thanks

I cannot do it on my board. But I will do it with the TI evaluation  board and I will let you know.

Regards,

Mathieu