Is it possible that the following workaround to this issue in the F2803x Errata will also work for the F2806x device?
Thanks,
Stuart
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Is it possible that the following workaround to this issue in the F2803x Errata will also work for the F2806x device?
Thanks,
Stuart
Hi Stuart,
Using the /2 bit in the '03x family results in no error because the ADCCLK ends up being 30MHz (or less if the SYSCLK < 60MHz). The '06x family uses the /2 by default to get an ADCCLK of 45MHz. In this case, the error is limited to about 4 LSBs, per the '06x errata. The ADC architecture is virtually identical between these devices, so if you run an '06x device at 30MHz or less I think you should get no measurable error. I am pretty sure there is a /4 enable on the '06x devices, so you could run at 22.5MHz and presumably have no error. (Note that all of this assumes you have enabled the non-overlap mode.)
Devin,
Thank you for the quick response. I have a few follow on questions specific to the product that we are working on:
Calculating the timing of sampling all of the ADC channels we need to sample and we are bit tight running the ADC at 22.5MHz.
1. If a SOC is triggered alone and there at least X time before and after any other SOC would trigger, is it still affected by the initial conversion errata? My normal sampling interval is 25 microseconds for all samples, but I need to sample one of those channels at 12.5 microsecond intervals (synchronous with the PWM update). So I am wondering if I have all ADC channels sample as a sequential set, and then have that additional individual channel sample occur by its own, is it affected by the initial conversion errata? The errata isn’t clear if it is caused by the SOC triggering itself, or the fact that more than one sample & conversion is occurring at the same time or back to back.
2. If the first SOC in a sequence has a very long sample time set along with the NONOVERLAP mode, is that a possible way to get past the initial conversion errata? I’m finding the 13 ADC cycles for conversion is what is taking up most of the time in my calculations since the sample time is only 7 ADC clocks, so the only way to reduce the conversion time is to run the ADC at a faster frequency.
Thanks,
Stuart