The F2837xD reference manual (SPRUHM8E) section 6.5 (Free Running Counter, p786) states that IPCCOUNTERH is latched on a read of IPCCOUNTERL to avoid a race condition between reading IPCCOUNTERL and IPCCOUNTERH in the event of an IPCCOUNTERL overflow. Figure 6-1 (p784) indicates there is a single set of IPCCOUNTERL and IPCCOUNTERH.
The scheme for reading the 64-bit timer is fine for a single CPU reading the IPC counter registers, but what happens in the event of both CPUs reading the IPC counter registers at the same time in the event of an IPCCOUNTERL overflow?
Here is an example (I am assuming the counter counts upwards):
1. CPU 1 reads IPCCOUNTERL as 0xFFFFFFFF. IPCCOUNTERH is latched as 0xFFFFFFFF
2. IPCCOUNTERL overflows to 0x00000000
3. CPU 2 reads IPCCOUNTERL as 0x00000000. IPCCOUNTERH is latched as 0x00000000
4. CPU 1 reads IPCCOUNTERH as 0x00000000
5. CPU 2 reads IPCCOUNTERH as 0x00000000
Therefore CPU1 has read the 64-bit timer as 0x00000000FFFFFFFF instead of 0xFFFFFFFFFFFFFFFF.
Is my logic correct, or is there a separate IPCCOUNTERH register for each CPU that is latched when that CPU reads IPCCOUNTERL, such that CPU1 reads 0xFFFFFFFFFFFFFFFF and CPU2 reads 0x0000000000000000 regardless of the interleaving of the reads by the two CPUs?
This question seems applicable to the F2837xD and F28M3x series
