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F28069 Reset pulse duration

Joe Zhu
Intellectual 2540 points

Hi Champion,

Now my customer meet a question about F28069 reset time, we find in 85°C temp, we use outside reset IC to control F28069 reset pin, we set if VDDIO below 3.1V, will trigger reset and find if reset held time is 400us, sometimes MCU cannot reset successful, we use a toggle GPIO to tracking whether user code run.

If we change held time(held in 0V in XRS) to 900us, it always run normally.

My question is how many time should keep reset low, then can confirm F28069 will run normally? I find datasheet have mention in table5-3, it just 32tc(OSCCLK), but now it seems not work.

Sencond question is in datasheet section5.4, we have a parameter "Supervisor reset release dalay time", test condition is Time after BOR/POR/OVR event is removed to XRS release, so what is the OVR means? Is it means outside reset source held XRS low time?

Thanks!

BR

Joe

  • 0
    TI__Guru 55700 points

    Joe,

    You should be following "Supervisor reset release delay time" and not tw(RSL2).

    tw(RSL2) is the amount of time XRSn is pulled low on WD reset etc. Since you are using an external supervisor circuit, you should be following Supervisor reset release delay time. So, wait for 800us and then release the device from reset for normal operation

    I'm not sure about OVR. I will get back on that soon.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Intellectual 2540 points
    Hi Manoj,

    Thanks! So if I use external supervisor, what's the minimun time I should keep XRS low to confirm system can run normaly? Expecially in high temperature environment like 85°C air temperature.

    Thanks!
  • 0 in reply to Joe Zhu
    TI__Guru 55700 points

    Joe,

    Yes, 800us should be good enough at high temp as well. Did you already try 800us at high temp?


    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Intellectual 2540 points
    Manoj,

    So what is the minimun time wo should keep in XRS pin? Is it 800us, customer should confirm this value. Now we test 1 chip, 800us is OK, but we not sure whether every one in this worst case, 800us is the shortest time?

    Thanks!
    BR
    Joe
  • 0 in reply to Joe Zhu
    TI__Guru 55700 points
    Joe,

    Minimum time to hold XRSn is 400us.

    Regards,
    Manoj
  • 0 in reply to Manoj Santha Mohan
    TI__Expert 7885 points
    Hi Joe,

    To reset the device via XRSn, the XRSn pin voltage needs to be driven below the max VIL level of the pin which is 0.8V.

    1. Can you capture the XRSn waveform on a scope when you reset the device?
    2. Does the XRSn voltage make it below 0.8V?
    3. Is the device tied to the XRSn pin an open-drain device?

    Best Regards,
    Adam Dunhoft
  • 0 in reply to Adam Dunhoft
    TI__Expert 7885 points
    This post was being handled offline and found that the issue was covered by the errata: "Oscillator: CPU Clock Switching to INTOSC2 May Result in Missing Clock Condition After Reset"

    It was also found that an extended reset pulse would allow the device to recover, but was not considered a workaround by TI per below:

    "The workaround stated in the errata is an actual workaround which prevents the device from going into the erroneous state and highlighted to be the valid workaround based on root cause. What you have found with the extended XRSn pulse is a recovery mechanism and is not considered a workaround as it does not prevent the device from entering that state. Since this elongated reset pulse is not considered a workaround, it would have never been pursued for any validation or characterization."

    Joe,

    If you have any further questions, please post them to this thread.

    Best Regards,
    Adam Dunhoft