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F2806x IIC

Hi Champs,

I have question about IIC whenthe module  working at salve modes.

Below are  the IIC user mannul--Operating Modes description,  so did it means if IIC module  working in Slave-receiver modes , when RSFULL = 1 , the SCL will be hold low? if  IIC module  working in Slave-transmitter mode , when XSMT = 0 , the SCL will be hold low?

If yes, when the SCL be hold low, how to release the SCL?

Except RSFULL = 1 and XSMT = 0 , any other case will hold the SCL  low?

 

Slave-receiver modes

The I2C module is a slave and receives data from a master.
All slaves begin in this mode. In this mode, serial data bits received on SDA are shifted in with
the clock pulses that are generated by the master. As a slave, the I2C module does not
generate the clock signal, but it can hold SCL low while the intervention of the device is
required (RSFULL = 1 in I2CSTR) after a byte has been received. See section Section 14.2.7
for more details.


Slave-transmitter mode

The I2C module is a slave and transmits data to a master.

This mode can be entered only from the slave-receiver mode; the I2C module must first receive
a command from the master. When you are using any of the 7-bit/10-bit addressing formats,
the I2C module enters its slave-transmitter mode if the slave address byte is the same as its
own address (in I2COAR) and the master has transmitted R/W = 1. As a slave-transmitter, the
I2C module then shifts the serial data out on SDA with the clock pulses that are generated by
the master. While a slave, the I2C module does not generate the clock signal, but it can hold
SCL low while the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has
been transmitted. See section Section 14.2.7 for more details.

  • Yes, SCL will be held low in those cases. Slaves have to accept and provide data when the master requests it. To release SCL in slave-receiver mode, read data from I2CDRR. To release SCL in slave-transmitter mode, write data to I2CDXR. To force a release without handling the data, reset the module using the I2CMDR.IRS bit.

    Those should be the only cases where SCL is held low.