• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 83 subscribers
  • Views 929 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F28377D ADC ppb delay cpu01 example code

Lisa Ding
Expert 6525 points

Hi Champs,

i ran F2837xD ADC delay capture example code and change PWM2 period to 4096 which is twice than PWM1. Both CMPA are 1024. As my understand, SOC0/SOC1 will trigger at TBCTR=1024. Therefore, first conversion should collide. However, i check the example code, the first detection is happen at conversion count = 8. If PPB miss the first conversion, according to my setting, ADC conversion should collide at 1,4,6,8,10,12...etc. It looks like we miss the 1,4,6 conversion. Could you please tell me is this the normal condition ? thanks.

  • 0
    TI__Guru 60865 points
    Hi Lisa,

    At the first trigger, both SOC0 and SOC1 are triggered. RR priority causes SOC0 to convert first. Since SOC0 won on priority, and we are detecting delays to SOC0, no additional delay is detected (but if you used a PPB pointed to SOC1, you would see that it was delayed). After both SOCs convert, SOC0 has priority due to RR pointer.

    The second trigger event occurs on SOC0 only. After SOC0 converts, RR pointer now gives priority to SOC1.

    At the third event, both SOC0 and SOC1 are triggered. You should see a delay here since SOC1 has priority. Looking at the example, I am not sure if the ePWMs are really completely synchronized though; I think they start one after the other, so it seems like maybe SOC0 should always win out.