How to make TI DSP as a slave

Mohammad,

We don't currently have any examples for the SPI configured as a Slave. You should be able to simply set SPICTL.MASTER_SLAVE to 0, and adjust the main code in the examples to wait rather than initiate the transfer.

If you run into any trouble with this please let us know. 

Thanks,
Mark

Responding here as I said I would in your other thread.

In addition to clearing the MASTER_SLAVE bit, you could also disable the TX FIFO and its interrupt since you don't plan on transmitting anything. You can disable loopback (SPICCR.SPILBK).

Have you tried running your code yet? Are you having a specific issue?

Whitney

I have set SPICCR.4 (Bit for SPILBK) to zero. But how can I disable the TX FIFO and its interrupt?? Is it by putting SPIFFTX.5 (TXFIENA bit) to zero?

Yes, that will disable the interrupt.

Whitney

Actually I have changed SPICTL.2 (Master/Slave) bit to 0, SPICCR.4 (SPILBK) bit to 0 and SPIFFTX.5 (TXFFIENA) bit to 0. But still I am not receiving any data from SPI.

Are you seeing the clock and data from the master? Can you verify that with a scope?
How are you handling the Chip Select on the Slave side? Are you toggling the signal properly or is it tied to ground?

-Mark

Great.

I am going to close this post. If you have any more questions, don't hesitate to create a new post.

-Mark

Thanks for your suggestions.

-Mohammad Arifur Rahman