Hello,
I am controlling four motors using the above processor. I have the ADC SOC's triggered on the respective PWM's. The EOC triggers an ADC interrupt. Each EOC is assigned one of the four ADC interrupts.
ADC-A, ADC-B and ADC-C are assigned to the A,B, and C phases of the motor (current sense) respectively. Interrupts are triggered when the EOC occurs on ADC-C. The ADC interrupt slots on ADC-C are the only ones that are used. (Well, I have interrupts being used on ADC-A, but this is for testing only).
So PIE group 1 and 10 are used.
The interrupts are firing, and at the end of each ISR, the PIE ACK is cleared and then the respective ADC interrupt is cleared.
But what I am seeing is that ADC-C INT1 and INT4 get stuck. If I, through the debugger, manually reset these lines, then, sometimes, things start working fine again for a while, but then one of those interrupts sticks and the ISR ceases to function.
I have put in counters in each ISR that suggest to me that the peripheral interrupt is always being cleared when an ISR runs. At no time does an ISR run and it happens to skip clearing the ADC-C INTx bit.
When the interrupt stops firing the ADC-C INTx bit is set, so it appears as though PIE is somehow missing an interrupt request.
I have poured over various documentation and I am unable to recognize any scenarios that would allow for this to happen.
Bottom line is that I think:
1. Each time an ISR runs, the ADC-C bits are cleared. (along with the PIE ACK bit in the group)
2. When the ISR stops firing, the corresponding ADC-C INTx is set, suggesting it was either not cleared from a previous ISR run, or it was set and the PIE didn't pick it up.
Perhaps there is a third possibility that I am missing here.
Once everything is up and running, I do not modify any of the PIE enable registers. Interrupts are disabled when any of the PIE registers are modified (with the exception of the PIE ACK register, it is modified only in ISRs however).
