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PLL setup in TMS320F28335

Srinivasan Pandian85
Prodigy 30 points

As per the reference guide www.ti.com/.../sprufb0d.pdf the procedure to change the PLL Control Register has the following steps:

1. Check if PLLSTS[MCLKSTS] is not equal to 1
2. Set PLLSTS[DIVSEL] to 0
3. Set PLLSTS[MCLKOFF] to 1
4. Set new PLLCR value
5. Wait for PLL to lock.

1. What are the implications if we skip steps 1, 2 and 3 in the above described procedure under normal condition (non-limp mode)?

2. What are the implications if we skip steps 1, 2 and 3 in the above described procedure under limp mode?

  • 0
    Guru 30330 points
    Srinivasan,

    I am going to look into this. When we provide a numbered list such as the one you mentioned, the order must be followed. If all steps are not followed, we cannot guarantee operation of the device. These steps are single register writes and should not take application time, as it is during initialization. Why would you want to skip these steps?

    Again, I am going to see if I can find any clarification as to what happens when these steps are not followed.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Prodigy 30 points

    Mark,

    One of our software had these steps skipped while configuring the PLL. We would like to access the impact and understand the behavior of the software in its current state.

    Thanks,

    -Srinivasan

  • 0 in reply to Mark Labbato
    Prodigy 30 points

    Hi Mark,

    Any updates on the requested clarification. We are waiting for your input, based on which we have to submit an analysis report to our customer.

    -Srinivasan

  • 0 in reply to Srinivasan Pandian85
    TI__Guru 55700 points

    Srinivasan,

    Sorry for late response. With Thanksgiving holiday here most of team members were on vacation so we didnt get to this question.

    I have forwarded your question to our designers. Will try to get an answer by end of this week.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Guru 55700 points

    Srinivasan,

    In non-limp mode:

    When missing clock logic is not disabled before PLL is locked, PLL may (or) may not lock properly and might eventually lead to functional failure of device.


    In limp mode:-

    When you write to PLLCR in limp mode, clocks are automatically swiches to OSCCLK and  since no OSCCLK is present, system (or) CPU will stop.


    Regards,

    Manoj