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TMS320F28377D ADC sequencing

Other Parts Discussed in Thread: CONTROLSUITE

Hi Everyone!

I have some peculiar behavior with regard to ADC sequencing.  I'm attempting to operate the AdcA and AdcC in 16 bit mode simultaneously as described in the user manual.  This is how:

AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 3; // SOC0-2 are high priority
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // EPwm2 SOC A starts all 3 ADCA conversions (one after the other)
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 7;
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 7;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // 0 is for adcina0/1 diff group, 2 is for adcina2/3 diff group,
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 2; // 3 is for adcina4/5 group
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 4;

AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // EPwm2 SOC A starts both ADCC conversions (one after the other)

AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 7;
AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; // 2 is for adcinc2/3 diff group, 4 is for adcina4/5 diff group,
AdccRegs.ADCSOC1CTL.bit.CHSEL = 4;

When I do this, I get results in AdcaResultRegs.ADCRESULT0 through ADCRESULT2 and AdccResultRegs.ADCRESULT0 and ADCRESULT1, but they're all of the wrong channels.  Adca seems to cycle through all three on all three SOCs, and Adcc has results from channel 2/3 on both SOCs all the time.  Burst Mode is disabled on both A and C.

AdcB and AdcD are both 12 bit, but they're not running at the time that A and C are running.  B and D are run simultaneously and trigger an EOC that I start A and C with.

Does anybody have any idea why the SOCs won't stick to the channels that I give them?

Justin

  • Hi Justin,

    I think your understanding of how things should operate is correct. I also don't see any obvious issues with the code snippet provided. Some thoughts on how to debug:

    -You may want to set a breakpoint after all your initializations but before the main loop starts, and then manually check the ADC settings in the expressions window when you hit this point. Ensure:
    --->Trigger and channel selects are as expected.
    --->Burst mode not enabled
    --->(Other ADC/ePWM settings?)
    -You can do the same as above, but set the breakpoint somewhere that will pause after your code has started running and you are actually collecting samples

    -What are you using to force the voltages on the ADC pins? What is the expected conversion result and what are you actually getting for each of these channels? Usually the best debug strategy is to use some type of DC source to provided a different DC voltage on all the channels and then to compare expected vs. actual conversions. (Since you have 5 differential channels, this takes 10 DC sources though)

    -If you are going to use high priority mode on ADCA you should also use it on ADCC. In this case, I think you may also want to setup SOC2 on ADCC as a dummy conversion to ensure that ADCA and ADCC always operate in lock-step. (Note that the ADCs operating out of lock-step will cause some noise issues in the conversions, not affect which channel is sampled where.
  • Hi Devin!

    Thanks much for the fast response!
    I've done as you said- all of the registers are as expected as far as I can tell. Specifically, the trigsel and chsel fields in the SOC registers don't change for sure. I am triggering the SOCs from an ePWM, so I checked those too and they seem proper.
    My application requires bidirectional sensing, so a 1.5V offset is built into my analog chains (and a 3V external reference). When I only sense one of the 3 channels, the result is beautiful- I get very close to 32768 (within 500 or so), unless I short the 1.5V offset to ground somewhere in my analog chain, in which case the ADC result jumps to zero until I release the short. The actual driver of the ADC pins is a differential driver with a bandwidth of about 20MHz.

    Even if I set up SOC 2 as a dummy conversion on AdcC, I still get a random channel on each ADCRESULTx when running.

    Any other ideas?

    Justin
  • Hi Justin,

    Where are you reading the channel results? Is this in an ISR for the ADC or ePWM?

    If you configure all 3 SOCs on each ADC for the same channel, do you get the same results in all 3 result registers? Are the results correct?

    If you reduce the number of SOCs to 1, do you get the correct results?

    If you disable one of the two ADCs, are the results correct?

    If you use the ControlSUITE example for ePWM sampling do you get the correct results from A0/A1? What if you change the channel to A2/A3 or A4/A5?
  • Hi Devin!

    Thanks again for helping me with this.

    I'm reading the channel results in an ISR triggered by ADC EOC.

    If I configure all 3 SOCs for the same channel, everything works.  All three results are the same, the results are correct, and they all change when I modify the input voltage.

    If I reduce the number of SOCs to 1 for each ADC (one for A and one for C), I also get the correct results for any channel that I program to.

    If I disable C and try to run A on all three channels, I get the same random channel assignment to all 3 ADCRESULTx registers.

    I've also found that it isn't completely random.  On the SOC that's supposed to be (is in the control register) channel 0, the results bounce between channel 2 and channel 4 every other cycle.  On the SOC that's supposed to be (is in the control register) channel 2, the results bounce between channel 0 and channel 4 every other cycle. On the SOC that's supposed to be (is in the control register) channel 4, the results bounce between channel 0 and channel 4 every other cycle.  I've found this by putting the results in a buffer during the ISR and graphing them.  I verified the above by changing the voltage on one at a time and watching the graph change.

    When I load the adc_soc_epwm_cpu01 project, it doesn't run well on my board- I had to make modifications.  I inserted a function to activate a DAC- that's what I use for the 1.5V offset :-).  Also, it was set up to be 12 bit- I changed it to 16 bit.  After that, it runs great, and all three channels come out fine.  What's more interesting is that when I alter the code to do all 3 conversions, same as in my code, all SOCs stay on their channels- everything behaves the way that I want it to.  I'll try to see what the differences are between my code and the sample.

    Does any of this help narrow things down?

    Justin

  • Hi Justin,

    I think this definitely narrows things down to a SW issue in your code....the device itself and the HW both seem to be ok. You are definitely going to want to focus on the ADC differences between your code and the modified example.

    If careful examination of the code doesn't work, one strategy that you could use to pinpoint the differences between your code and the modified example would be:
    -set a breakpoint somewhere after initializations have run
    -open the memory browser and set the location to the base address of the ADCA registers
    -Save the contents of the ADCA registers memory to a file
    If you do this for both the modified example with the 3 channels and your code with 3 channels you can then diff the files and start investigating where the differences are.

    I also am not sure how your results could get crossed without changing the channel select register. You should definitely search your code for any errant instances of the channel select being written. I think you can also create a hardware watchpoint to effectively trigger a dynamic breakpoint when changes to the channel select register occur:

    processors.wiki.ti.com/.../Hardware_Breakpoints_and_Watchpoints_for_C28x_in_CCS
  • Solved- I had the clock prescale values in the ADCs set incorrectly to /1. That produces an ADC clock of 100Mhz. When I used a prescale of /2 (50 Mhz, which is the max stated in the data sheet), everything worked as I expected. Thank you for helping me with this. Your suggestion of specific sample code is what did it- this error was found by comparing my code to the ControlSuite code and finding the differences.

    Justin
  • Justin,

    Glad you got it to work. Good luck with the rest of your development!