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Delfino byte addressing on 32 bit EMIF, Asynch mode

EEngineer505
Prodigy 590 points

I am trying to confirm the ability to address to the byte level on the Asynch mode and SDRAM mode when using 32 bit wide EMIF on EMIF1.

 

It appears it supports byte level addressing.

 

However, on Asynch mode it gets more confusing.

 

The referenced figures only add to the confusion.

It's my understanding the core processor(s) of the Delfino are 16 bit word oriented, so I want to make sure I do not guess wrong on this.

Historically TI has assumed the 16 bit word perspective so thoroughly that they rarely clarified it anywhere in the documentation.

For all I know the concept here is that it can use a byte wide device as its interface to the 16 bit word interface.

The question is, can I write to a byte on a 32 bit wide EMIF bus in Asynch mode?  Changing just that byte and no other?

  • 0
    TI__Guru** 116971 points

    Hi,

    As you rightly pointed out, C28x is 16bit core hence byte access is not supported. The specific note you have mentioned about asynch interface is about how to connect address pins if using 8bit external device. Even though C28x CPU only supports 16bit/32bit access, you can configure the EMIF to support 8bit external device and in that case EMIF splits the 16bit access from CPU into 2 byte access. You can not have 16 or 32bit external device and only update a byte of 16bit/32bit location.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Prodigy 590 points

    Thank you Vivek for your advisement.

    I do have additional questions regarding configuration of SDRAM mode interface:

    I have a 32 bit wide SDRAM IS42S32800J-7BLI  (attached)IS42S32800J-7BLI.pdf
    With two CS, 9 column address pins and 12 row address pins and 4 Byte mask bits.

    My questions relate to SDRAM_CR
    “14 NM R/W 0h Narrow mode.
    Set to 1 when system bus width to memory bus width is 2:1 for SDR SDRAM.
    Set to 0 when system bus width to memory bus width is 1:1 for SDR SDRAM.”

    Since the bus width and the memory device have the same width, that would suggest setting it to ‘0’.
    But how does it know my device size and the desired configuration width of the bus (both 32 bit wide)?

    “6-4 IBANK R/W 2h Defines number of banks inside connected SDRAM devices:
    000: 1 bank SDRAM devices.
    001: 2 bank SDRAM devices.
    010: 3 bank SDRAM devices.”  = = = = I believe this is actually 4 banks. ??

    2-0 PAGESIGE R/W 0h Defines the internal page size of connected SDRAM devices:
    000: 256-word pages requiring 8 column address bits.
    001: 512-word pages requiring 9 column address bits.
    010: 1024-word pages requiring 10 column address bits.
    011: 2048-word pages requiring 11 column address bits.

    = = = I believe what is actually being controlled for here is the number of column address bits.

    “Using the settings of the IBANK and PAGESIZE fields of the SDRAM configuration register (SDRAM_CR), the EMIF determines which bits of the logical address will be mapped to the SDRAM row, column, and bank addresses.”

    I am not clear there is enough information given to allow the Delfino to configure for my 32 bit wide SDRAM.
    Where do I configure the EMIF1 to be 32 bit wide?

  • 0 in reply to EEngineer505
    TI__Guru** 116971 points

    Hi,

    Since the bus width and the memory device have the same width, that would suggest setting it to ‘0’.
    But how does it know my device size and the desired configuration width of the bus (both 32 bit wide)?

    System bus is 32bit and it's internal setting of EMIF which is taken care in hardware. Based on this configuration, EMIF IP understands the external device configuration (16bit or 32bit).

    010: 3 bank SDRAM devices.”  = = = = I believe this is actually 4 banks. ??

    You are right. This should be 4 bank. We will correct this in next release. Thank you for this info.

    = = = I believe what is actually being controlled for here is the number of column address bits.

    That is correct.

    I am not clear there is enough information given to allow the Delfino to configure for my 32 bit wide SDRAM.
    Where do I configure the EMIF1 to be 32 bit wide?

    As mentioned in Ist point, once you configured NM field to '0', EMIF IP understands that external device is 32bit wide.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 116971 points
    Hi Shawn, Let us know if you have any further query.