Hi,
dealing with fast SPI communication on the F28069 acting as SPI Master , we came to problems in properly receiving answers from the slave at higher clock rates, i.e. 22,5 MHz
Setup is
SpiaRegs.SPICCR.all =0x000F | (0x40 & 0x00); // Reset on, rising edge, 16-bit char bits | Clock Polarity
SpiaRegs.SPICTL.all =0x0006 | (0x08 & 0xFF); // Enable master mode, normal phase, | Clock Phase
which means Clock Polarity is 0, Clock Phase is 1, which commonly is denominated as SPI Mode 0 and was expected to meet slave behaviour.
When running an SPI clock of 11,25MHz, Slave data is read correctly, whereagainst at 22.5 Mhz, received data appears bitshifted by one bit, though an SPI anylyser claimed everything to behave correctly.
We now wanted to find out the reason and investigated the situation more in detail. We were suspicious on the sample timing of the SOMI signal, expected sample time of a signal in mode 0 shoud be the rising edge of the clock.. Therefor we generated small pulses with random timing on the SOMI line and triggered the scope whenever received data was != 0. Please find according screen shots below.
- magenta colour: SPI clock
- cyan colour: SIMO signal with data pattern 0xAAAA for reference purposes
- yellow colour: SOMI signal of special kind as stated above.
Result at 11.25 Mhz: sample sensitivity lies in middle between falling and rising edge
Result at 22.5 Mhz: sample sensitivity lies at falling edge of clock signal, expected was at rising edge.
Conclusion: in sampling the SOMI signal there seems to be kind of sample delay independent from the clock frequency in a magnitude of 20ns.
Could you please comment?
Kind regards
Wolfgang Zehetmair
