Hello Team,
I have a customer who is needing further explanation on how the the start bit is synchronized if an external transmitter is sending continuous stream of frames (assuming that both micro-controllers are setup in Asynchronous mode and NOT in multiprocessor modes)
" The main thing I am trying to understand: How does the Receiver differentiate between Start bit and any other Data bit in a Frame when SCI is setup as regular UART and external Transmitter is sending a continuous stream of Frames without any delay between two successive message Blocks.
Case 1:
In the below attached diagram, if the UART 2 powers up first and starts listening and then the UART 1 powers up and starts transmitting, then there should not be any issue on detecting the Start bit since line was Idle and then Receiver detects four consecutive SCICLK periods of zero on the line. From this point on, the UART 2 Receiver should be able to read continuous stream of Frames without any issue.
Case 2:
Now, if the UART 1 powers up first and starts transmitting continuous stream of frames, when the UART2 powers up, how does it differentiate a Start bit from a random Data bit since line is never Idle for any amount of time?
Note: I have started on a project and inherited a similar implementation. The development team has verified that the driver works even when they break the communication link during the transmission, the Receiver somehow is able to synchronize with start of Frame. But no one quite understands how? In case 2, it seems that the Receiver should continuously encounter Frame Overrun errors but in reality it does not. I will really appreciate if you can provide an explanation for this behavior. "
Thank you for your assistance with this.
Sincerely,
Kishen
