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F28379D datasheet question

Lisa Ding
Expert 6525 points


Hi Champs,

My customer asked about Reset Lo(RLS1) max/min time. in datasheet, it showed only typ time. Do we have RLS1 max/min time ? 

For ADC 12-bit single-ended mode, our SPEC based on VREFHI=2.5v. Do we have ENOB SPEC base on VERFHI=3,3v ? 

thanks for your reply in advance.

  • 0
    TI__Guru 60865 points

    Hi Lisa,

    For ADC ENOB, 2.5V VREFHI is worst case.  Increasing the VREFHI voltage gives a larger range for the internal ADC noise to spread out over, so you would see a very slight improvement in SNR of maybe 1dB.  

    Do be cautious, however, because VREFHI < VDDA is a hard requirement; ADC performance will be negatively impacted if VREFHI = 3.3V and VDDA = 3.3V and VDDA starts to drift lower than 3.3V.  For this reason, we recommend a 3.0V reference instead.  Alternately, you could use a configurable regulator for VDDA and VDDIO to set these rails a couple percent higher than 3.3V. 

  • 0 in reply to Devin Cottier
    TI__Expert 6525 points
    Hi Devin,
    I see. Thanks for reply. Do we have data for Reset Lo(RLS1) max/min time ? thank you!