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XCLKOUT on F28M36

KarlheinzRieber
Intellectual 550 points

Other Parts Discussed in Thread: CONTROLSUITE

Dear all,

My F28M36 run both, M3 and C28, at 125MHz

    SysCtlClockConfigSet(SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 12)
                                     | (SYSCTL_SPLLFMULT_M & 0x200)
                                     | SYSCTL_SYSDIV_1
                                     | SYSCTL_M3SSDIV_1
                                     | SYSCTL_XCLKDIV_1);

I tried to give control of the XCLKOUT pin (GPIO34) both to the M3 and C28. However I always get a quarter of 125MHz, say 31.25 MHz, at the XCLKOUT pin.

Is it possible to get a lower output frequency than 25MHz at XCLKOUT, without changing the 125MHz?


Thanks a lot for your answers!

  • 0
    TI__Genius 15260 points

    Hi Karlheinz,

    The information I am referencing can be seen in Figure 1-12 of the TRM found here:

    One way to get a divider greater than /4 would be to set the XCLKOUT to the C28SYSCLK using the XPLLCLKOUTDIV register.  Then use the XCLKDIV register to divide the frequency down further.  See the image below.

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    Intellectual 550 points
    Dear Kris,

    thank you for your answer.

    I am still confused. How can I change the XCLKOUTDIV in the CXCLK register? According to the green color in the figure, this should be done on th C28 side. How can I change this register in software? The SysCtrlRegs structure (taken from ControlSuite) does not have this register (0x7010). Must it be changed by the M3 software? If yes, how can I do it?

    Regards,
    Karlheinz
  • 0 in reply to KarlheinzRieber
    TI__Genius 15260 points

    Karlheinz,

    This looks like this may be a header file bug. On the C28x, using the Memory Browser window in Code Composer Studio, can you try writing values of 0, 1, and 2 to 0x7010 and see if you observe any changes? I do not have silicon with me to test it today, but if you cannot test it then I will look next week.

    I'll also notify someone from our software team to have a look at it.

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    Intellectual 550 points

    Kris,

    thanks again for your answer.

    I tried to change CXCLK (0x7010) in the C28 memory browser. Unfortately it does not change the XCLKOUT outpin. Still I have 31.25MHz which is a quarter of the 125MHz at which both cores are running.

    I also tried *(unsigned int*)0x7010 = 2;
    in the C28 void InitSysCtrl(void) function, without success.

    In chapter 1.8.7 of the TRM is written: "Note that only the master subsystem can configure the XCLKOUT divider."
    According to figure 1.12 and according to table 1-38 the CXCLK register is in the C28 memory. It seems strange to me ;-)

    Regards,

    Karlheinz

  • 0 in reply to KarlheinzRieber
    TI__Genius 15260 points
    Hi Karlheinz,

    Thank you for checking that. We are investigating this and will let you know as soon as we have a definite answer.

    Regards,

    Kris
  • 0 in reply to Kris Parrent
    Intellectual 550 points
    Hello Kris,

    I did some more measurements...

    Both cores are running at 125MHz.

    If the pin is controlled by the C28 core and XPLLCLKCFG register is set to 0x01 then I get at GPIO34:
    31.25MHz if 0x7010 is set to 0
    62.5MHz if 0x7010 is set to 1
    125MHz if 0x7010 is set to 2
    High Signal if 0x7010 is set to 3

    The XPLLCLKCFG register does not care. And here the /4 divider in front of GPIO_MUX1 (figure 1-12 of TRM) is not active...



    If the pin is controlled by the M3 core and XPLLCLKCFG register is set to 0x01 then I get at GPIO34:
    31.25MHz if XPLLCLKCFG is set to 3
    31.25MHz if XPLLCLKCFG is set to 2
    31.25MHz if XPLLCLKCFG is set to 1 (content of 0x7010 does not change any behaviour)
    Low Signal if XPLLCLKCFG is set to 0

    So here the /4 divider is always active but CXCLK register is ignored...

    Figure 1-12 does not seem to be accurate... How can I get less than 25MHz out off this pin?

    Thanks a lot,

    Karlheinz
  • 0 in reply to KarlheinzRieber
    TI__Genius 15260 points

    Karlheinz,

    I hope to have an answer by the end of the day.  Can you tell me what revision of silicon you're using?  Please provide the register value of the REVID register seen here:

    Thanks,

    Kris

  • 0 in reply to Kris Parrent
    TI__Genius 15260 points
    Karlheinz,

    Based on my experimentation and your results seem to agree, it seems that the output of the XCLKOUTDIV mux goes directly to the pin, and that the input to XPLLCLKCFG[1] is the undivided C28SYSCLK. I have passed this along to our design team for verification. I will get back to you as soon as I have an answer.

    Regards,

    Kris
  • 0 in reply to Kris Parrent
    Intellectual 550 points
    Kris,

    yes, the documentation seems different than the silicon...

    The PARTID is 0xFF and the REVID is Ox01.

    Thanks,

    Karlheinz
  • 0 in reply to KarlheinzRieber
    TI__Genius 15260 points

    Karlheinz,

    Thank you for the information. I have confirmed with our design team that the implementation is different than the diagram in the TRM.

    Here is a diagram I very quickly marked up to make the implementation clearer:

    As you can see, with these options the maximum divider on XCLKOUT is going to be /4 which is going to be 31.25 MHz in your case.  Is it a requirement for your application to have XCLKOUT under 25 MHz?

    I have filed tickets for both the C28x header files and TRMs to be updated with our findings on their next release.  Thank you for your patience while we get this corrected.

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    Intellectual 550 points
    Kris,

    I verified your answer and thank you for your help.

    Unfortunately we need 25MHz or less, so we can not use this pin as expected. So we have to do a redesign and we loose money and time. I suggest TI to check the documentation more thoroughly before they release it...

    Best regards,

    Karlheinz
  • 0 in reply to KarlheinzRieber
    TI__Genius 15260 points

    Karlheinz,

    You may be able to use the APWM feature of the ECAP1 to accomplish what you are looking to do. It is a simple PWM waveform that will have some divide down of the system clock depending on how you configure the peripheral.  This is on GPIO34 so there would not be a board redesign.

    Regards,

    Kris