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No Activity on CS2/CS3/CS4 Lines

Hello, I am having some issues and could use some direction.

I am configuring the EMIF1 (from CPU1) to access a FPGA; and using the Async mode of 32 bit operation.

I'm accessing the CS2/CS3/CS4 space which is mapped into FPGA using TI’s sample project “emif1_16bit_asram” and “emif1_32bit_sdram”as references.
The EMIF1 is successfully configured to access an 32Mb sdram on CS0 as well.

The problem is, even in the different EMIF settings,  there is no activity on CS2/CS3/CS4 lines, even when observed through a scope.

I tried the “emif1_16bit_asram” project on TI’s DevBoard, and monitoring the CS2/GPIO34 pin and also could not see any activity (the pin go de-active high and stay high).

Can you please advise me where it is going wrong? 

Thank you.