CLA Watchdog Reset vs Emulator Reset

Hi Vivek,

Thanks for the suggestion.  My application code for setting up the CLA does enable the CLA clock after the memcpy() for CLA code and prior to writing any CLA registers in the Delfino by:

    SysCtlPeripheralEnable((uint32_t) SYSCTL_PERIPH_CLA1);

and in the Piccolo by:

    SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1;

Also, I have checked the MVECT values in the Expressions window, which show they have been programmed to the correct address/offset.  I believe the MVECT registers cannot be written unless the CLA clock is enabled.

Any other ideas?

Best Regards,

Joseph

Hi Vishal,

Thanks for the suggestions.  I have read that thread that you linked, but I went over it again more carefully per your suggestion.

1) I believe I am copying the CLA program. Excerpts from my linker .cmd:

Hi Vishal,

I have read that post, but I went over it again more carefully per your suggestion.

1) I believe I have to be copying the CLA program as the linker file specifies loading it into flash and there is no other way for the CLA program to be in RAM after loading from the emulator other than the memcpy() shown below.  Excerpts from my linker .cmd:

MEMORY
{
PAGE 0 :   /* Program Memory */
    L3DPSARAM   : origin = 0x009000, length = 0x001000     /* L3   DPSARAM, CSM secure, CLA Program RAM, within SP range */
    OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
    #ifdef FLASH_BOOT
    // restrict from full length of 0x1FF80 to sector A/B/C/D/E length of 0x13F80
    FLASH       : origin = 0x3E4000, length = 0x013F80     /* on-chip FLASH */
    #else
    // restrict from full length of 0x1FF80 to sector A/B/C length of 0xBF80
    FLASH       : origin = 0x3EC000, length = 0x00BF80     /* on-chip FLASH */
    #endif

    Cla1Prog                : LOAD = FLASH
                              RUN  = L3DPSARAM                                            /* Link to CLA Program RAM */
                              LOAD_START(_cla1prog_load_start),
                              LOAD_SIZE(_cla1prog_load_size),
                              RUN_START(_cla1prog_run_start),
                              PAGE = 0, ALIGN(4)

And from the CLA initialization function prior to writing to enablging the clock to the CLA and writing to the MemCfgRegs and Cla1Regs:

    (void) memcpy(&cla1prog_run_start, &cla1prog_load_start,
        (int16_t) &cla1prog_load_size);

2) Elliott (original poster of above link) had an issue on power up which I don't think applies since my case does not involve power cycling.  Power should be  stable unless the watchdog reset somehow causes the voltage to droop.

3) You mentioned copying .cla_const which I was not doing, but I believe invalid constants in my application only causes an invalid PWM value to be written by the CLA, but should not prevent the CLA from running.  To rule it out, I went ahead and tried copying from flash with the following addition to the linker .cmd:

PAGE 1 :   /* Data Memory */

    M01SARAM    : origin = 0x000000, length = 0x000800     /* on-chip RAM block M0, M1, within SP range */
    PIEVECT     : origin = 0x000D00, length = 0x000100     /* peripheral interrupt expansion */
    CLA2CPU     : origin = 0x001480, length = 0x000080     /* Part of PF0 - CLA to CPU Message RAM */
    CPU2CLA     : origin = 0x001500, length = 0x000080     /* Part of PF0 - CPU to CLA Message RAM */
    L01DPSARAM  : origin = 0x008000, length = 0x000C00     /* L0-1 DPSARAM, CSM secure, within SP range */
    L2DPSARAM   : origin = 0x008C00, length = 0x000400     /* L2 DPSARAM, CSM secure, within SP range */

    .const_cla              : LOAD = FLASH                                       PAGE = 0
                              RUN  = L2DPSARAM                                   PAGE = 1 /* Link to CLA Program RAM */
                              LOAD_START(_cla1const_load_start),
                              LOAD_SIZE(_cla1const_load_size),
                              RUN_START(_cla1const_run_start),
                              ALIGN(4)

And the following in the CLA initialization:

    (void) memcpy(&cla1prog_run_start, &cla1prog_load_start,
        (int16_t) &cla1prog_load_size);
    (void) memcpy(&cla1const_run_start, &cla1const_load_start,
        (int16_t) &cla1const_load_size);

I think those were the only 3 issues suggested from the above link and your reply above, however I don't think any of them are causing the CLA non-responsiveness after watchdog reset in this case.  Any other ideas on what is different between emulator and watchdog reset that could cause this?

Best Regards,

Joseph

There shouldn't be much difference between the resets except for the route through the boot code; at least to my knowledge that is the only difference. After a watchdog reset and the IACK instruction do you see the MIRUN bit for that task get set? Can you connect to the CLA and see where the execution is at  - even if you dont connect to the CLA you can inspect the Cla1Regs.MPC to see if it changes - that would mean the CLA is executing some code.

Vishal_Coelho said:

There shouldn't be much difference between the resets except for the route through the boot code; at least to my knowledge that is the only difference. After a watchdog reset and the IACK instruction do you see the MIRUN bit for that task get set? Can you connect to the CLA and see where the execution is at  - even if you dont connect to the CLA you can inspect the Cla1Regs.MPC to see if it changes - that would mean the CLA is executing some code.