This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi guys,
I don't have technical problem, but I wan't to give some feedback to C2000 designers. As some of you know, SCI baud rate calculation for some c2000 mcu's (at least for 28335, 28377,28379) is like this:
SCI baud rate = LSPCLK / ((BRR+1)*8) , where BRR is between 0 to 65535. So in theory, you can have 65536 different baud rates. But because of the calculation method, baud rate values are decreasing (like) logarithmically. So in practice, you have limited options for high baud rates, but (unnecessary) too much options for low baud rates. I wrote a code which prints BRR and it's baudrate value. You can see that for higher bauds (> 1 Mbaud) you have only few options (actually 24 different baud rate options are available), but for lower baud rates, you have plenty options (you have about 63700 different options for baud rates less than 9600, which is unneccessary)
I know that this baud rate calculation is not a random equation, it comes from the design of the chip, however, I hope the designers will change the SCI IP block, so that we can have better baud rate distribution. My question is: Is there any platform or link that I can send my feedback?
*************************** LSPCLK = 200000000 ***************************
BRR: 1 - BaudRate: 12500000
BRR: 2 - BaudRate: 8333333
BRR: 3 - BaudRate: 6250000
BRR: 4 - BaudRate: 5000000
BRR: 5 - BaudRate: 4166667
BRR: 6 - BaudRate: 3571429
BRR: 7 - BaudRate: 3125000
BRR: 8 - BaudRate: 2777778
BRR: 9 - BaudRate: 2500000
BRR: 10 - BaudRate: 2272727
BRR: 11 - BaudRate: 2083333
BRR: 12 - BaudRate: 1923077
BRR: 13 - BaudRate: 1785714
BRR: 14 - BaudRate: 1666667
BRR: 15 - BaudRate: 1562500
BRR: 16 - BaudRate: 1470588
BRR: 17 - BaudRate: 1388889
BRR: 18 - BaudRate: 1315789
BRR: 19 - BaudRate: 1250000
BRR: 20 - BaudRate: 1190476
BRR: 21 - BaudRate: 1136364
BRR: 22 - BaudRate: 1086957
BRR: 23 - BaudRate: 1041667
BRR: 24 - BaudRate: 1000000
BRR: 25 - BaudRate: 961538
BRR: 26 - BaudRate: 925926
BRR: 27 - BaudRate: 892857
BRR: 28 - BaudRate: 862069
BRR: 29 - BaudRate: 833333
BRR: 30 - BaudRate: 806452
BRR: 31 - BaudRate: 781250
BRR: 32 - BaudRate: 757576
BRR: 33 - BaudRate: 735294
BRR: 34 - BaudRate: 714286
BRR: 35 - BaudRate: 694444
BRR: 36 - BaudRate: 675676
BRR: 37 - BaudRate: 657895
BRR: 38 - BaudRate: 641026
BRR: 39 - BaudRate: 625000
BRR: 40 - BaudRate: 609756
BRR: 41 - BaudRate: 595238
BRR: 42 - BaudRate: 581395
BRR: 43 - BaudRate: 568182
BRR: 44 - BaudRate: 555556
BRR: 45 - BaudRate: 543478
BRR: 46 - BaudRate: 531915
BRR: 47 - BaudRate: 520833
BRR: 48 - BaudRate: 510204
BRR: 49 - BaudRate: 500000
BRR: 50 - BaudRate: 490196
BRR: 51 - BaudRate: 480769
BRR: 52 - BaudRate: 471698
BRR: 53 - BaudRate: 462963
BRR: 54 - BaudRate: 454545
BRR: 55 - BaudRate: 446429
BRR: 56 - BaudRate: 438596
BRR: 57 - BaudRate: 431034
BRR: 58 - BaudRate: 423729
BRR: 59 - BaudRate: 416667
BRR: 60 - BaudRate: 409836
BRR: 61 - BaudRate: 403226
BRR: 62 - BaudRate: 396825
BRR: 63 - BaudRate: 390625
BRR: 64 - BaudRate: 384615
BRR: 65 - BaudRate: 378788
BRR: 66 - BaudRate: 373134
BRR: 67 - BaudRate: 367647
BRR: 68 - BaudRate: 362319
BRR: 69 - BaudRate: 357143
BRR: 70 - BaudRate: 352113
BRR: 71 - BaudRate: 347222
BRR: 72 - BaudRate: 342466
BRR: 73 - BaudRate: 337838
BRR: 74 - BaudRate: 333333
BRR: 75 - BaudRate: 328947
BRR: 76 - BaudRate: 324675
BRR: 77 - BaudRate: 320513
BRR: 78 - BaudRate: 316456
BRR: 79 - BaudRate: 312500
BRR: 80 - BaudRate: 308642
BRR: 81 - BaudRate: 304878
BRR: 82 - BaudRate: 301205
BRR: 83 - BaudRate: 297619
BRR: 84 - BaudRate: 294118
BRR: 85 - BaudRate: 290698
BRR: 86 - BaudRate: 287356
BRR: 87 - BaudRate: 284091
BRR: 88 - BaudRate: 280899
BRR: 89 - BaudRate: 277778
BRR: 90 - BaudRate: 274725
BRR: 91 - BaudRate: 271739
BRR: 92 - BaudRate: 268817
BRR: 93 - BaudRate: 265957
BRR: 94 - BaudRate: 263158
BRR: 95 - BaudRate: 260417
BRR: 96 - BaudRate: 257732
BRR: 97 - BaudRate: 255102
BRR: 98 - BaudRate: 252525
BRR: 99 - BaudRate: 250000
BRR:100 - BaudRate: 247525
...
...
..
BRR:1822 - BaudRate: 9600
BRR:1823 - BaudRate: 9594
BRR:1824 - BaudRate: 9589
BRR:1825 - BaudRate: 9584
BRR:1826 - BaudRate: 9579
BRR:1827 - BaudRate: 9573
BRR:1828 - BaudRate: 9568
BRR:1829 - BaudRate: 9563
BRR:1830 - BaudRate: 9558
BRR:1831 - BaudRate: 9552
BRR:1832 - BaudRate: 9547
BRR:1833 - BaudRate: 9542
...
...
Kadir,
Your concerns were passed to our Architecture team. Redesign of the existing SCI module is not possible, as it is almost 2 decades old now. Our Concerto devices (in production) have another flavor of an asynchronous port, UART, in addition to the SCI. This UART has a fractional divider as well, which may address your concerns. A similar peripheral would be part of our next generation device as well.
Dear Hareesh,
I thank you for your attention and contacting c2000 design team. Unfortunately I can't use concerto, I have to use delfino series, because it's more suitable to my application.
Morover, it's a shame that TI uses a 20 years old IP block in their newest, state of the art processors like F28377 and F28379, and doesn't want to change that ineffiecient block. I say inefficient because there are 63713 different speed options for speed less than 9600 and only 24 options for speed more than 1 Mbaud. I understand the concept "if it works, don't change it" but it not valid for this case. Thank you anyway.
Hakan
hello Kadir
i am working with TMS320F28379D( LAUNCHXL-F28379D development kit).
my problem is i want 20Khz PWM for my application
as per my knowledge baud rate (TBPRD = 10000)
but when i run the program it is suporting only (TBPRD = 1250) for 20Khz
this is my program:
void InitEPwm1Example()
{
// // Setup TBCLK //
EPwm1Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm1Regs.CMPA.bit.CMPA = 1250; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = 1250;
// // Setup counter mode //
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,
// down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up
// count
EPwm1Regs.AQCTLB.bit.ZRO= AQ_SET; // Clear PWM1B on event B,
// down count
// // Interrupt where we will change the Compare Values //
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event