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280x atomic access to 32-Bit CPU Timers 0/1/2

Galen Seitz
Intellectual 485 points

If I use an instruction that performs a 32 bit read of one of the TIMERxTIM registers, is this access guaranteed to be atomic with respect to counter rollover?  In other words, is there any chance that the upper and lower words of the read data will be inconsistent.  I'm using a 28015.

thanks,

galen

 

  • 0
    TI__Guru* 93800 points

    Galen Seitz said:

    If I use an instruction that performs a 32 bit read of one of the TIMERxTIM registers, is this access guaranteed to be atomic with respect to counter rollover?  In other words, is there any chance that the upper and lower words of the read data will be inconsistent.  I'm using a 28015.

    thanks,

    galen

    If you perform a 32-bit access to a volatile variable then the access will not be broken up into two 16-bit accesses.  You can double check that this is happening by looking at the disassembly in code composer studio. 

    -Lori

     

  • 0 in reply to Lori Heustess
    Intellectual 485 points

    Sorry I wasn't more clear.  This really wasn't a compiler question.  I just want to confirm that a movl from a TIMERxTIM register cannot be corrupted due to counter rollover.

    thanks,

    galen


  • 0 in reply to Galen Seitz
    TI__Guru* 93800 points

    Galen Seitz said:
    This really wasn't a compiler question.  I just want to confirm that a movl from a TIMERxTIM register cannot be corrupted due to counter rollover.

    Yes, the MOVL will perform a single 32-bit read so you will get the timer value (all bits) at that instance.

    Regards,

    Lori