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F28M36P63C2: F28M36P63C reset needed after SEU/SEFI events

TISL
Expert 4630 points
Part Number: F28M36P63C2

Hello,

My customer is facing some issues related to SEU/SEFI phenomena, in his end application.

- To solve the interruption problems due to the SEFI, they are wondering if it's possible to make a reset of 1.2V (VREG12EN), while maintaining the 1.8V and 3.3V.

- Is it possible to share the source code of the boot SW? Can we modify it or deactivate it?

Regards,

Sébastien

  • 0
    TI__Expert 7885 points
    Hello Sebastian,

    What do you mean by resetting 1.2V VREG? VREG12EN is a pin which is pulled high or low depending on supply method of 1.2V VDD rail.

    Is your customer supplying 1.2V externally or are they using the internal 1.2V VREG?

    Best Regards,
    Adam Dunhoft
  • 0 in reply to Adam Dunhoft
    TI__Expert 4630 points

    Hello Adam,

    They've tried to make the reset with their external 1.2V. It solves their issue; which is not the case if they use the XRS reset: the chip stays frozen in the boot of the M3.

    They will try, in a second time, to use our internal regulator and the VREG12EN.

    But the question is: is it a good advise to reset the digital core through this "hardware" way?

    Is it possible to share the source code of the boot SW? Can we modify it or deactivate it?

    Regards,

  • 0 in reply to TISL
    TI__Expert 7885 points
    Hello Sebastien,

    Reset question: This is not the recommended way of resetting the device. If you are using internal VREG and set VREGENZ to high, it will most likely reset the VDDIO and VDD rails but there has not been any characterization of this method (drive level, drive time, etc.) so it would not be supported.

    Are both reset pins tied together (XRSn & ARSn)?

    Boot SW question: I will let another team member respond to this.

    Best Regards,
    Adam Dunhoft
  • 0 in reply to TISL
    TI__Mastermind 30255 points
    Sebastien,

    In regards to the boot SW, it can't be modified, disabled or bypassed. The boot source code is not publicly released, they will have to continue referencing the TRM for the boot flow details or pursue a NDA with TI to get the source code.

    Best Regards
    Chris
  • 0 in reply to Christopher Chiarella
    TI__Expert 4630 points

    Hi Chris,

    The NDA is under process.

    Could you send me the boot source code in private?

    Regards,

  • 0 in reply to TISL
    TI__Mastermind 30255 points
    Sébastien,

    Great! We are going through the process of getting the software licensed and packaged for handoff. I will reach out once this is ready, please be patient with us as this can take up to two or so weeks. I'll do my best to move it along quickly!

    Best Regards
    Chris
  • 0 in reply to Adam Dunhoft
    TI__Expert 4630 points

    Hello Adam,

    Coming back on the reset question:

    Just to clarify some points, the customer ties together the XRSn and ARSn, but through this way the reset doesn't work.

    They succeed to do a Reset through VREG12EN, knowing that they are using an external 1.2V

    Can you describe what are the differences between XRS/ARS reset and 1.2V reset?

    As they use an external 1.2V, do you confirm that the risks are the same as your description above?

    Regards,

  • 0 in reply to TISL
    TI__Expert 7885 points
    Hello,

    Yes. The risk still exists. If the customer is using an external 1.2V supply to supply the VDD rail and the VREG12EN pin is pulled low then there will be contention on the VDD rail as it is trying to be supplied by both internal and external supplies. This could cause damage to the F28 or external supply IC. Resetting the device in this manner is not supported. I am actually not quite sure how the customer is resetting the device in this manner if the external 1.2V supply always stays active unless the voltage on that 1.2V supply is drooping low enough to cause the device to go into reset.

    The description for both XRSn and ARSn can be found on pages 36 and 190 of www.ti.com/.../f28m36p63c2.pdf

    The XRSn pin is the reset pin for the digital subsystem while the ARSn pin is the reset for the analog subsystem.

    Best Regards,
    Adam Dunhoft
  • 0 in reply to Adam Dunhoft
    TI__Expert 4630 points
    Adam,

    Understood for the 1.2V reset.
    But can we clarify what's the difference between a "Power Reset" and a "XRS/ARS Reset"? as the chip doesn't react with the XRS/ARS Reset, it means that some parts of the chip are not concerned by this Reset.

    Other thing: I would need to share the source code located in the OTP.
    Can you provide it?

    Regards,
  • 0 in reply to TISL
    TI__Expert 7885 points
    Hello,

    You can find more information about the resets in the TRM on p. 85 www.ti.com/.../spruhe8d.pdf

    The table here shows that the resets should be the same. Are you sure that the XRSn pin and ARSn pin are being driven all the way to zero and held for the required amount of time to reset the device? [tw(RSL2) Pulse duration, XRS low for 32tc(OCK) cycles]

    Are you looking for BROM code?

    Best Regards,
    Adam Dunhoft
  • 0 in reply to Adam Dunhoft
    TI__Expert 4630 points
    Hello,

    Not BROM code but TI reserved OTP memory.
    Where you can find, for exemple, the Factory Settings and Calibration Function of the ADC.

    Regards,
  • 0 in reply to TISL
    TI__Expert 4630 points
    Hi Adam,

    The customer has always this pending question regarding the way to power the chip; even if we know that it hasn't been caracterized, can we explain the internal behavior:

    "We use external power supplies for each supply 1.2V, 1.8V and 3.3V. Internal LDOs are deactivated -> pull-up on VREG12EN and VREG18EN.
    What are the risks to switch off only the 1.2V external power supply during more than 200ms, with 3.3V and 1.8V still externally supplied,
    and then to switch on the 1.2V external power supply ?
    What are the internal links between the supplies ?
    Will the microcontroller re-start normally with this test?"

    Regards,
  • 0 in reply to TISL
    TI__Expert 7885 points
    Hello Sebastian,

    Basically what you are doing is power-cycling the 1.2V rail. This will cause a reset the same as a POR. The device should restart normally, as long as the 1.2V supply is powered all the way down.

    Can you please send the schematic regarding the XRSn and ARSn pin? Have you tried resetting the device in the manner stated in the datasheet/TRM?

    You can find more information about the resets in the TRM on p. 85 www.ti.com/.../spruhe8d.pdf

    The table here shows that the resets should be the same. Are you sure that the XRSn pin and ARSn pin are being driven all the way to zero and held for the required amount of time to reset the device? [tw(RSL2) Pulse duration, XRS low for 32tc(OCK) cycles].

    Best Regards,
    Adam Dunhoft