Nested Interrupts in TMS320F2802x

 one place to find this would be in the workshop 

http://processors.wiki.ti.com/index.php/C2000_Piccolo_One-Day_Workshop_Module_2#Interrupts

I seem to remember an application note with software example called 'DSP280x Software Prioritized Interrupts'.  The reprioritization was accomplished by nesting.  I'll try tracking it down.

That is in www.ti.com/controlsuite

make sure you choose the Piccolo F2802x (or whichever processor you are using) and look here

C:\ti\controlSUITE\device_support\f2802x\v127\DSP2802x_examples_ccsv4\sw_prioritized_interrupts

Thanks for the response. I looked through the code but still couldn't figure out if the code described prioritizing interrupts, e.g. telling the cpu which interrupt to process after the current one has finished, or actually stopping execution of the current interrupt.

However, the following answer was given on another thread that turned out to answer my confusion just in case anyone looks at this thread later:

the default operating mode of the C28x regarding interrupts is "No - Nested". However, you can overrule this into a "Nested" system by your own code. 

The default no-nested sequence is this:

ISR1:

1. Hardware context save, including INTM and IER

2. Hardware disables INTM and the corresponding IER-bit

3. Your ISR1 code is executed, including ACK of the PIE

4. Hardware context restore, including the status of INTM and IER as they were set upon entry.

A nested  interrupt - system would look like this:

ISR1:

1. Hardware context save, including INTM and IER

2. Hardware disables INTM and the corresponding IER-bit

3. You enable those IER-lines, which you would like to be able to interrupt ISR1, while ISR1 is still running. Also, enable INTM now. Do also a PIE-ACK here, if your higher prioritized INT is within the same PIE group.

4. Execute your ISR1 code here.  If your higher prioritized ISR (which you enabled in step3) is triggered and it's ISR will interrupt the running ISR1 code.

5. Hardware context restore, including the original status of INTM and IER upon entry at step1.

ISR2:

Same sequence as for ISR1. In step 3 you can qualify other interrupt sources to be of higher priority  than ISR2.

Thanks to all!

Hi,

Thanks for this post. I am using F28335 DSP.

I am trying to create a nested interrupt with CPU Timer 0 as high priority and SCIRX as 2nd priority ISR. So if the code is in the CPU Timer 0 interrupt and the SCIRX interrupt occurs, I would like the code to service SCIRX after CPU Timer 0 ISR is complete.  If the CPUTimer0 occurs while SCIRX ISR is being serviced, I would like to just jump from the SCIRX ISR to the CPUTimer0 ISR, instead of waiting for SCIRX ISR to finish.

I understand in order to do this we need to set IER bits for higher priority interrupts, do PIE-ACK, and also set INTM in the ISR function as explained in prev. post. 

From the previous post  step 2, it says "Hardware disables INTM and the corresponding IER-bit". I did not see the IER bits being cleared upon entering the CPU Timer 0 ISR though.  Is the "IER" referring to the CPU interrupt enable register or PIERx?

 Below is my code for the two ISRs:

------------------------------------------------------------------

interrupt void cpu_timer0_isr(void)

{

//1. Hardware context save including INTM and IER

//2. Hardware disables INTM and the corresponding IER-bit

volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; //temp copy the PIEER regs

//Is the line below required? [also some issue with Real-time debug ISR]

IER =0x0; //Clear IER                                      

IER |= M_INT1;   // Enable Interrupts in ISR Group 1

PieCtrlRegs.PIEACK.all = 0x01;   // Enable PIE interrupts from Group 1

EINT;

// Insert ISR Code here.......

    CpuTimer0.InterruptCount++;

    updateLCD(Vllrms, Iacrms,Vdc);

    DELAY_US (10000);

// End ISR Code

   // Restore registers saved:

DINT; //INTM enabled by hardware after exiting ISR func.

PieCtrlRegs.PIEIER1.all = TempPIEIER;

//Hardware context restore, including orig. status of INTM, and IER. 

}

---------------------

interrupt void sciaRxFifoIsr(void)

{   

    volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; //temp copy the PIEER regs

    IER = 0x0;

IER |= M_INT1;      // Enable Interrupts in ISR 1                                        

PieCtrlRegs.PIEACK.all = 0x1;   // Enable  PIE interrupts from Group 1

EINT;

//ISR Code goes here....

PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack for Group 9

DINT; //INTM enabled by hardware after exiting ISR func.

PieCtrlRegs.PIEIER1.all = TempPIEIER;

}

David,

to step2 of my explanation in an earlier thread:

the IER and INTM are cleared (disabled) by hardware - you will not find any instructions in the code.

If the CPU accepts an interrupt, IER and INTM are pushed into stack automatically. Just after that step INTM and the corresoponding bit in IER are disabled automatically.