TMS320F28377S: TMS320F28377S: C2000 / TMS320F28377S => SPI Timing Jitter between CLK ans MOSI

Hello Folks,

i have the SPI running on a TMS320F28377S and have a time jitter between CLK ans MOSI.
I have configured the SPI to put out 12 bits per character, and for a test i use a bit coded value of 0b110010101100.
On the scope i see the last bits are missing, while the clock starts to early.
Is there something i haven´t considered in the initialisation?
Below see the scope´s screenshot and my SPI_Init and ISR.

best regards!

#define SPI_BRR        ((200E6 / 4) / 500E3) - 1

void DACSink::Init()
{
	EALLOW;
	//ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0;
	//SpiaRegs.SPICCR.bit.HS_MODE = 0x1;
    //
    // Enable internal pull-up for the selected pins
    //
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    // Comment out other unwanted lines.
    //
    //GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;  // Enable pull-up on GPIO16 (SPISIMOA)
    //GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;  // Enable pull-up on GPIO18 (SPICLKA)
	GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0;  // Enable pull-up on GPIO16 (SPISIMOA)
	GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0;  // Enable pull-up on GPIO18 (SPICLKA)

    //
    // Set qualification for selected pins to asynch only
    //
    // This will select asynch (no qualification) for the selected pins.
    // Comment out other unwanted lines.
    //
    GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO16 (SPISIMOA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO18 (SPICLKA)

    //
    //Configure SPI-A pins using GPIO regs
    //
    // This specifies which of the possible GPIO pins will be SPI functional
    // pins.
    // Comment out other unwanted lines.
    //
    GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // Configure GPIO16 as SPISIMOA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // Configure GPIO18 as SPICLKA
    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Configure GPIO16 as SPISIMOA
    GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Configure GPIO18 as SPICLKA

	 //
	    // Initialize SPI FIFO registers
	    //
	SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
	SpiaRegs.SPIFFTX.bit.SPIFFENA = 1;
	SpiaRegs.SPIFFTX.bit.TXFIFO = 0; //reset fifo pointer
	SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
	SpiaRegs.SPIFFTX.bit.TXFFIENA = 1;
	SpiaRegs.SPIFFTX.bit.TXFFIL = 0;


	 SpiaRegs.SPIFFTX.bit.TXFIFO=1;
	 SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
    // Initialize SPI-A

    // Set reset low before configuration changes
    // Clock polarity (0 == rising, 1 == falling)
    // 16-bit character
    // Enable loop-back
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpiaRegs.SPICCR.bit.SPICHAR = (12-1);
    SpiaRegs.SPICCR.bit.SPILBK = 0;

    // Enable master (0 == slave, 1 == master)
    // Enable transmission (Talk)
    // Clock phase (0 == normal, 1 == delayed)
    // SPI interrupts are enabled
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpiaRegs.SPICTL.bit.TALK = 1;
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
    SpiaRegs.SPICTL.bit.SPIINTENA = 1;

    // Set the baud rate
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    SpiaRegs.SPIPRI.bit.FREE = 1;

    // Release the SPI from reset
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;

    PieCtrlRegs.PIEIER6.bit.INTx2 = 1;     // Enable PIE Group 6, INT 2
    IER=M_INT6;                              // Enable CPU INT6
    PieVectTable.SPIA_TX_INT = &spiAint;

 EDIS;
}

__interrupt void spiAint(void)
{
	DELAY_US(1000);
	GpioDataRegs.GPACLEAR.bit.GPIO19 = 1;
	SpiaRegs.SPITXBUF=3244;
	SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;  // Clear Interrupt flag
	PieCtrlRegs.PIEACK.all|=M_INT6;       // Issue PIE ACK
	GpioDataRegs.GPASET.bit.GPIO19 = 1;
}