TMS320F28377D: CPU1: Telling [CpuSysRegs.RESC.bit.XRSn=1] to user code like main().

Hideaki Nambu

Mastermind 9165 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: CONTROLSUITE

Hello,

Could you please advise how user code evaluates the bit CpuSysRegs.RESC.bit.XRSn ?

I made the attached project and observed the bit.

As the result, the bit was cleared when "SETC OBJMODE" was executed:

[F2837xD_CodeStartBranch.asm]
Ln-67          SETC OBJMODE        ;Set OBJMODE for 28x object code
        $../F2837xD_CodeStartBranch.asm:67:78$(), wd_disable:
082668:   561F        SETC         OBJMODE    ; *** Here RESC changes from 0xC000002 to 0xC0000000.

I would think a solution would be saving the bit before the line, but I wonder there would be an easy way, could you pelase advise ?.

/cfs-file/__key/communityserver-discussions-components-files/171/blinky_5F00_cpu01_5F00_v130_5F00_01temp.zip

This project was modified from the controlSUITE v130 CPU1 blinky.

over 9 years ago

0 Vivek Singh over 9 years ago

TI__Guru** 117051 points

Hideaki-san,

Change to OBJMODE should not clear this status bit. If you are viewing this register in watch window then please refresh it before executing this code and see if it is already cleared.

Regards,
Vivek Singh

0 Hideaki Nambu over 9 years ago in reply to Vivek Singh

Mastermind 9165 points

Vivek,
I appreciate your reply. I tested again an understood that my test was not something wrong. The bit CpuSysRegs.RESC.bit.XRSn is cleared in somewhere boot ROM.
I'd like to back to customer' request. Could you please advise how to report the reset cause XRSn to main() ?

0 Vivek Singh over 9 years ago in reply to Hideaki Nambu

TI__Guru** 117051 points

Hideaki-san,

I tested again an understood that my test was not something wrong. The bit CpuSysRegs.RESC.bit.XRSn is cleared in somewhere boot ROM.

That is correct. BOOTROM clears the status of POR and XRSn.

Could you please advise how to report the reset cause XRSn to main() ?

Please let me know how are they planning to use this info? Are they trying differentiate between XRSn and WD reset or something else? Are they also want to differentiate POR?

Regards,

Vivek Singh

0 Hideaki Nambu over 9 years ago in reply to Vivek Singh

Mastermind 9165 points

Vivek,
Thank you for your inputs. I'll talk to my customer.

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TMS320F28377D: CPU1: Telling [CpuSysRegs.RESC.bit.XRSn=1] to user code like main().