Tool/software: Code Composer Studio
#include "F28x_Project.h" // Device Headerfile and Examples Include File
#include "math.h"
#include "IQmathLib.h"
extern void InitSysCtrl(void);
extern void InitPieVectTable(void);
extern void InitPieCtrl(void);
interrupt void ePWM1A_compare_isr(void);
#pragma DATA_SECTION(sine_table,"IQmathTables");
_iq30 sine_table[512];
void main(void)
{
InitSysCtrl();
InitPieCtrl(); // basic setup of PIE table
InitPieVectTable(); // copy default ISR’s into PIE
EALLOW;
PieVectTable.EPWM1_INT = &ePWM1A_compare_isr;
WdRegs.WDCR.all = 0x00AF;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // ePWM1A
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // enable pull-up
EDIS;
EPwm1Regs.TBCTL.all = 0; // default values
EPwm1Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 1
EPwm1Regs.TBCTL.bit.CTRMODE = 2; // up-down mode
EPwm1Regs.AQCTLA.all = 0x0006; // ZRO=set; PRD=clear
EPwm1Regs.TBPRD = 2250; // 500 kHz PWM frequency
// TBPRD = fcpu / (2* fpwm * CLKDIV * HSPCLKDIV)
// TBPRB = 90 MHz / (2 * 500 kHz * 1 * 1)
EPwm1Regs.CMPA.bit.CMPA = 1125; // initial duty 50 %
EPwm1Regs.AQCTLA.all = 0x0060;
// CMPA up = set; CMPA down = clear
EPwm1Regs.ETSEL.all = 0;
EPwm1Regs.ETSEL.bit.INTEN = 1; // enable ePWM1 int
EPwm1Regs.ETSEL.bit.INTSEL = 5; // CMPA down match
EPwm1Regs.ETPS.bit.INTPRD = 1; // 1st event
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // ePWM1
IER |= 4; // enable INT3
EINT; // global int enable
while(1)
{
EALLOW;
WdRegs.WDKEY.all = 0x55; // service key #1
WdRegs.WDKEY.all = 0xAA; // service key #2
EDIS;
}
}
interrupt void ePWM1A_compare_isr(void)
{
static unsigned int index = 0;
EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD - _IQsat(_IQ30mpy((sine_table[index]+_IQ30(0.9999))/2,EPwm1Regs.TBPRD),EPwm1Regs.TBPRD,0);
if (index++ >511) index = 0;
EPwm1Regs.ETCLR.bit.INT = 1; // clear ePWM1 interrupt flag
PieCtrlRegs.PIEACK.all = 4; // ACK for PIE group 3 int
}