I am using TMS320F28377S, and configuring Global PWM Load Function.
I have some questions about this function.
1:
I use GLDCNT for updating registers(CMPA,CMPB,etc...) timing adjustment.
And I checked GLDCNT value at ePWM1 by like
(GCNT1 = EPwm2Regs.GLDCTL.bit.GLDCNT;)
Then,I noticed GLDCNT value is 0 at A point and 1 at B point (Please see the following code)
------------------------------------------------------------------------------
EALLOW;
EPwm2Regs.GLDCTL.all = 0x0183U;
EPwm2Regs.GLDCFG.all = 0x0002U;
EDIS;
EPwm2Regs.TBCTL.all = 0x8003U;
EPwm2Regs.TBPRD = 999;
(A point)
EPwm2Regs.TBCTL.bit.CTRMODE = 0U;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0x1U;
(B point)
---------------------------------------------------
So I interpreted Initial GLDCNT value is 1 because that value changes 0 to 1 when TBCLKSYNC = 1U;
Is this interpretation is true?
2:
When ePWM3 configuring is following
EALLOW;
EPwm3Regs.GLDCTL.all = 0x0181U;/* Load registers when TBCTR = 0U,and GLDPRD = 3U */
EPwm3Regs.GLDCFG.all = 0x0002U;
EDIS;
EPwm3Regs.TBPRD = 999;
EPwm3Regs.TBCTL.bit.CTRMODE = 0U;
GLDCNT value changes like
0→1(when TBCLK = 1U)→2(after 10us)
and TBCTR changes like this
0→0(when TBCLK = 1U,TBCTR starts counting up (C point) )→999(reaches TBPRD value)→0(afetr 10us,GLDCNT value changes 1 to 2)
Does this mean first TBCTR = 0U (C point) is not treated as TBCTR = Event ?
3:When configuring ePWMs like below
#include <math.h>
#include <F2837xS_Cla_typedefs.h>
#include <F2837xS_device.h>
#pragma CODE_SECTION(InitFlash_Bank0, "ramfuncs");
#pragma CODE_SECTION(InitFlash_Bank1, "ramfuncs");
#define IMULT_12 12
#define IMULT_20 20
#define IMULT_40 40
#define FMULT_0 0
#define PLLCLK_BY_2 1
#define INT_OSC2 0
#define XTAL_OSC 1
#define INT_OSC1 2
#define AUXCLKIN 4
#define PLLCLK_BY_126 63
static void InitFlash_Bank0(void);
static void InitFlash_Bank1(void);
static void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel);
static void SysIntOsc1Sel(void);
static void SysIntOsc2Sel(void);
static void SysXtalOscSel(void);
static void InitPeripheralClocks();
static void InitGpio();
static void InitPieCtrl(void);
static void InitPieVectTable(void);
static void DisableDog(void);
static void ISR_ILLEGAL(void);
static void MemCopy(Uint16* DestAddr, Uint16* SourceAddr, Uint32 size );
extern Uint16 RamfuncsRunStart;
extern Uint16 RamfuncsLoadStart;
extern Uint32 RamfuncsLoadSize;
void InitSystem(void);
Uint16 InitPWM(Uint16 CarrierFrequency, float32 DeadtimePonRaw, float32 DeadtimeNonRaw,
Uint16 InitPinP, Uint16 InitPinN, Uint16 Offset);
Uint16 SetPhase_Duty_PWM(float32 Duty_P, float32 Duty_S);
void F28x_usDelay(Uint32);
Uint16 CNT1 = 0U;
Uint16 CNT2 = 0U;
Uint16 CNT3 = 0U;
Uint16 CNT4 = 0U;
Uint16 CNT5 = 0U;
Uint16 CNT6 = 0U;
Uint16 CNT7 = 0U;
Uint16 CNT8 = 0U;
Uint16 CNT9 = 0U;
Uint16 CNT10 = 0U;
Uint16 CNT11 = 0U;
Uint16 CNT12 = 0U;
Uint16 CNT13 = 0U;
Uint16 CNT14 = 0U;
Uint16 CNT15 = 0U;
Uint16 CNT16 = 0U;
Uint16 CNT17 = 0U;
Uint16 CNT18 = 0U;
Uint16 CNT19 = 0U;
Uint16 CNT20 = 0U;
Uint16 CNT21 = 0U;
Uint16 CNT22 = 0U;
Uint16 CNT23 = 0U;
Uint16 CNT24 = 0U;
Uint16 CNT25 = 0U;
Uint16 CNT26 = 0U;
Uint16 CNT27 = 0U;
Uint16 CNT28 = 0U;
Uint16 CNT29 = 0U;
Uint16 CNT30 = 0U;
Uint16 CNT31 = 0U;
Uint16 CNT32 = 0U;
Uint16 CNT33 = 0U;
Uint16 CNT34 = 0U;
Uint16 CNT35 = 0U;
Uint16 CNT36 = 0U;
Uint16 GCNT0 = 0U;
Uint16 GCNT1 = 0U;
Uint16 GCNT2 = 0U;
Uint16 GCNT3 = 0U;
Uint16 GCNT4 = 0U;
Uint16 GCNT5 = 0U;
Uint16 GCNT6 = 0U;
Uint16 GCNT7 = 0U;
Uint16 GCNT8 = 0U;
Uint16 GCNT9 = 0U;
Uint16 GCNT10 = 0U;
Uint16 GCNT11 = 0U;
Uint16 GCNT12 = 0U;
Uint16 GCNT13 = 0U;
Uint16 GCNT14 = 0U;
Uint16 GCNT15 = 0U;
Uint16 GCNT16 = 0U;
Uint16 GCNT17 = 0U;
Uint16 GCNT18 = 0U;
Uint16 GCNT19 = 0U;
Uint16 GCNT20 = 0U;
Uint16 GCNT21 = 0U;
Uint16 GCNT22 = 0U;
Uint16 GCNT23 = 0U;
Uint16 GCNT24 = 0U;
Uint16 GCNT25 = 0U;
Uint16 GCNT26 = 0U;
Uint16 GCNT27 = 0U;
Uint16 GCNT28 = 0U;
Uint16 GCNT41 = 0U;
Uint16 GCNT42 = 0U;
Uint16 GCNT43 = 0U;
Uint16 GCNT44 = 0U;
Uint16 GCNT45 = 0U;
Uint16 GCNT46 = 0U;
Uint16 GCNT47 = 0U;
Uint16 GCNT48 = 0U;
Uint16 ICNT1 = 0U;
Uint16 ICNT2 = 0U;
Uint16 ICNT3 = 0U;
Uint16 ICNT4 = 0U;
Uint16 ICNT5 = 0U;
Uint16 ICNT6 = 0U;
float32 u = 0.9F;
float32 v = 0.9F;
float32 w = 0.0F;
Uint16 cnt_int = 0U;
Uint16 debugswitch = 4U;
#pragma INTERRUPT(Phase_Duty)
void Phase_Duty(void)
{
PieCtrlRegs.PIEACK.all = 0xFFFFU;
{
if(cnt_int == 0U)
{
SetPhase_Duty_PWM(0.9,0.9);
cnt_int = 1U;
}
else if(cnt_int == 1U)
{
SetPhase_Duty_PWM(-0.9,-0.9);
cnt_int = 0U;
}
}
EPwm1Regs.ETCLR.all = 0x1U;
}
int main(void)
{
__disable_interrupts();
InitSystem();
InitPWM(100,10,10,1,1,0);
__enable_interrupts();
EALLOW;
F28x_usDelay((Uint32)(5 * 40L) - 2);
GpioCtrlRegs.GPADIR.bit.GPIO10 = 1U;
CNT1 = EPwm1Regs.TBCTR;
GCNT1 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
CNT2 = EPwm2Regs.TBCTR;
GCNT2 = EPwm3Regs.GLDCTL.bit.GLDCNT;
CNT3 = EPwm3Regs.TBCTR;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT41 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT4 = EPwm4Regs.TBCTR;
GCNT3 = EPwm5Regs.GLDCTL.bit.GLDCNT;
CNT5 = EPwm5Regs.TBCTR;
GCNT4 = EPwm6Regs.GLDCTL.bit.GLDCNT;
CNT6 = EPwm6Regs.TBCTR;
ICNT1 = EPwm3Regs.ETPS.bit.INTCNT;
EDIS;
F28x_usDelay((Uint32)(5 * 40L) - 2);
EALLOW;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
GCNT5 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GCNT6 = EPwm3Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT7 = EPwm5Regs.GLDCTL.bit.GLDCNT;
GCNT8 = EPwm6Regs.GLDCTL.bit.GLDCNT;
ICNT2 = EPwm3Regs.ETPS.bit.INTCNT;
EDIS;
CNT7 = EPwm1Regs.TBCTR;
CNT8 = EPwm2Regs.TBCTR;
CNT9 = EPwm3Regs.TBCTR;
CNT10 = EPwm4Regs.TBCTR;
GCNT42 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT11 = EPwm5Regs.TBCTR;
CNT12 = EPwm6Regs.TBCTR;
F28x_usDelay((Uint32)(5 * 40L) - 2);
EALLOW;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
GCNT9 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GCNT10 = EPwm3Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT11 = EPwm5Regs.GLDCTL.bit.GLDCNT;
GCNT12 = EPwm6Regs.GLDCTL.bit.GLDCNT;
ICNT3 = EPwm3Regs.ETPS.bit.INTCNT;
EDIS;
CNT13 = EPwm1Regs.TBCTR;
CNT14 = EPwm2Regs.TBCTR;
CNT15 = EPwm3Regs.TBCTR;
CNT16 = EPwm4Regs.TBCTR;
GCNT43 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT17 = EPwm5Regs.TBCTR;
CNT18 = EPwm6Regs.TBCTR;
F28x_usDelay((Uint32)(5 * 40L) - 2);
EALLOW;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
GCNT13 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GCNT14 = EPwm3Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT15 = EPwm5Regs.GLDCTL.bit.GLDCNT;
GCNT16 = EPwm6Regs.GLDCTL.bit.GLDCNT;
ICNT4 = EPwm3Regs.ETPS.bit.INTCNT;
EDIS;
CNT19 = EPwm1Regs.TBCTR;
CNT20 = EPwm2Regs.TBCTR;
CNT21 = EPwm3Regs.TBCTR;
CNT22 = EPwm4Regs.TBCTR;
GCNT44 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT23 = EPwm5Regs.TBCTR;
CNT24 = EPwm6Regs.TBCTR;
F28x_usDelay((Uint32)(5 * 40L) - 2);
EALLOW;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
GCNT17 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GCNT18 = EPwm3Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT19 = EPwm5Regs.GLDCTL.bit.GLDCNT;
CNT29 = EPwm5Regs.TBCTR;
GCNT20 = EPwm6Regs.GLDCTL.bit.GLDCNT;
ICNT5 = EPwm3Regs.ETPS.bit.INTCNT;
CNT25 = EPwm1Regs.TBCTR;
CNT26 = EPwm2Regs.TBCTR;
CNT27 = EPwm3Regs.TBCTR;
CNT28 = EPwm4Regs.TBCTR;
GCNT45 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT30 = EPwm6Regs.TBCTR;
EDIS;
F28x_usDelay((Uint32)(5 * 40L) - 2);
EALLOW;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
GCNT21 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GCNT22 = EPwm3Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT23 = EPwm5Regs.GLDCTL.bit.GLDCNT;
CNT31 = EPwm5Regs.TBCTR;
CNT33 = EPwm4Regs.TBCTR;
GCNT46 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT35 = EPwm1Regs.TBCTR;
GCNT24 = EPwm6Regs.GLDCTL.bit.GLDCNT;
ICNT6 = EPwm3Regs.ETPS.bit.INTCNT;
EDIS;
F28x_usDelay((Uint32)(5 * 40L) - 2);
EALLOW;
GpioDataRegs.GPASET.bit.GPIO10 = 1UL;
GCNT25 = EPwm2Regs.GLDCTL.bit.GLDCNT;
GCNT26 = EPwm3Regs.GLDCTL.bit.GLDCNT;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1UL;
GCNT27 = EPwm5Regs.GLDCTL.bit.GLDCNT;
CNT32 = EPwm5Regs.TBCTR;
CNT34 = EPwm4Regs.TBCTR;
GCNT47 = EPwm4Regs.GLDCTL.bit.GLDCNT;
CNT36 = EPwm1Regs.TBCTR;
GCNT28 = EPwm6Regs.GLDCTL.bit.GLDCNT;
EDIS;
while(1)
{}
return 0;
}
Uint16 SetPhase_Duty_PWM(float32 Duty_P, float32 Duty_S)
{
Uint16 ret = 0U;
if(Duty_P > 1 || Duty_P < -1 || Duty_S > 1 || Duty_S < -1 )
{ ret = 1U; }
else
{
Uint32 Peak = 0UL;
Uint16 DutyIntPP = 0U;
Peak = (EPwm1Regs.TBPRD + 1UL);
DutyIntPP = (Uint16)((Duty_P + 1.0F) * Peak * 0.5 - 1U);
EPwm3Regs.CMPA.bit.CMPA = DutyIntPP;
EPwm2Regs.CMPA.bit.CMPA = DutyIntPP;
ret = 0U;
}
return ret;
}
Uint16 InitPWM( Uint16 CarrierFrequency, float32 DeadtimePonRaw, float32 DeadtimeNonRaw,
Uint16 InitPinP, Uint16 InitPinN, Uint16 Offset)
{
Uint16 IntDBRED = 0U;
Uint16 IntDBFED = 0U;
Uint16 ret = 0U;
IntDBRED = (Uint16)(2*DeadtimePonRaw);
IntDBFED = (Uint16)(2*DeadtimeNonRaw);
if(IntDBFED < 3U || IntDBRED < 3U)
{ ret = 1U; }
else
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.HRPWM = 0x1U;
CpuSysRegs.PCLKCR2.bit.EPWM1 = 0x1U;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 0x1U;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 0x1U;
CpuSysRegs.PCLKCR2.bit.EPWM4 = 0x1U;
CpuSysRegs.PCLKCR2.bit.EPWM5 = 0x1U;
CpuSysRegs.PCLKCR2.bit.EPWM6 = 0x0U;
EDIS;
EPwm1Regs.ETSEL.all = 0x1101U;
EPwm1Regs.ETCLR.all = 0x000DU;
EPwm1Regs.ETPS.all = 0x1101U;
EPwm2Regs.ETSEL.all = 0x1101U;
EPwm2Regs.ETCLR.all = 0x000DU;
EPwm2Regs.ETPS.all = 0x1101U;
EPwm3Regs.ETSEL.all = 0x1101U;
EPwm3Regs.ETCLR.all = 0x000DU;
EPwm3Regs.ETPS.all = 0x1101U;
EPwm4Regs.ETSEL.all = 0x1101U;
EPwm4Regs.ETCLR.all = 0x000DU;
EPwm4Regs.ETPS.all = 0x1101U;
EPwm5Regs.ETSEL.all = 0x1101U;
EPwm5Regs.ETCLR.all = 0x000DU;
EPwm6Regs.ETPS.all = 0x1101U;
EPwm6Regs.ETCLR.all = 0x000DU;
EPwm6Regs.ETPS.all = 0x1101U;
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO8 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO2 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO3 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO4 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO4 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO5 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO5 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0U;
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U;
EPwm1Regs.GLDCTL.all = 0x0183U;
EPwm2Regs.GLDCTL.all = 0x0183U;
EPwm3Regs.GLDCTL.all = 0x0181U;
EPwm4Regs.GLDCTL.all = 0x0187U;
EPwm5Regs.GLDCTL.all = 0x0187U;
EPwm6Regs.GLDCTL.all = 0x0187U;
EPwm1Regs.GLDCFG.all = 0x0000U;
EPwm2Regs.GLDCFG.all = 0x0002U;
EPwm3Regs.GLDCFG.all = 0x0002U;
EPwm4Regs.GLDCFG.all = 0x0004U;
EPwm5Regs.GLDCFG.all = 0x0002U;
EPwm6Regs.GLDCFG.all = 0x0002U;
EDIS;
EPwm1Regs.TBCTL.all = 0x8003U;
EPwm1Regs.PCCTL.all = 0x0U;
EPwm1Regs.TBPRD = (Uint32)( 100000 / (CarrierFrequency) ) - 1;
EPwm2Regs.TBCTL.all = 0x8003U;
EPwm2Regs.PCCTL.all = 0x0U;
EPwm2Regs.TBPRD = (Uint32)( 100000 / (CarrierFrequency) ) - 1;
EPwm3Regs.TBCTL.all = 0x8003U;
EPwm3Regs.PCCTL.all = 0x0U;
EPwm3Regs.TBPRD = (Uint32)( 100000 / (CarrierFrequency) ) - 1;
EPwm4Regs.TBCTL.all = 0x8003U;
EPwm4Regs.PCCTL.all = 0x0U;
EPwm4Regs.TBPRD = (Uint32)( 100000 / (CarrierFrequency) ) - 1;
EPwm5Regs.TBCTL.all = 0x8003U;
EPwm5Regs.PCCTL.all = 0x0U;
EPwm5Regs.TBPRD = (Uint32)( 100000 / (CarrierFrequency) ) - 1;
EPwm6Regs.TBCTL.all = 0x8003U;
EPwm6Regs.PCCTL.all = 0x0U;
EPwm6Regs.TBPRD = (Uint32)( 100000 / (CarrierFrequency) ) - 1;
EPwm1Regs.AQCTLA.all = 0x0012U;
EPwm2Regs.AQCTLA.all = 0x0012U;
EPwm3Regs.AQCTLA.all = 0x0012U;
EPwm4Regs.AQCTLA.all = 0x0012U;
EPwm5Regs.AQCTLA.all = 0x0012U;
EPwm6Regs.AQCTLA.all = 0x0012U;
EPwm1Regs.AQSFRC.all = 0U;
EPwm1Regs.AQCSFRC.all = 0U;
EPwm2Regs.AQSFRC.all = 0U;
EPwm2Regs.AQCSFRC.all = 0U;
EPwm3Regs.AQSFRC.all = 0U;
EPwm3Regs.AQCSFRC.all = 0U;
EPwm4Regs.AQSFRC.all = 0U;
EPwm4Regs.AQCSFRC.all = 0U;
EPwm5Regs.AQSFRC.all = 0U;
EPwm5Regs.AQCSFRC.all = 0U;
EPwm6Regs.AQSFRC.all = 0U;
EPwm6Regs.AQCSFRC.all = 0U;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 2U;
EPwm1Regs.CMPA.bit.CMPA = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm1Regs.CMPB.bit.CMPB = 1UL;
EPwm1Regs.CMPC = 750U;
EPwm1Regs.CMPD = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0U; /* CMPAShadow */
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0U; /* CMPBShadow */
EPwm1Regs.CMPCTL2.bit.SHDWCMODE = 0U; /* CMPCShadow */
EPwm1Regs.CMPCTL2.bit.SHDWDMODE = 0U; /* CMPDShadow */
EPwm1Regs.TBCTL.bit.PRDLD = 0U; /* TBPRDShadow */
EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 1U; /* DBFEDShadow */
EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 1U; /* DBREDShadow */
EPwm1Regs.DBCTL.bit.HALFCYCLE = 1U;
EPwm1Regs.DBCTL.bit.IN_MODE = 0U;
EPwm1Regs.DBCTL.bit.OUT_MODE = 3U;
EPwm1Regs.DBCTL.bit.POLSEL = 2U;
EPwm1Regs.DBCTL.bit.DEDB_MODE = 0U;
EPwm1Regs.DBCTL.bit.OUTSWAP = 0U;
EPwm1Regs.TBCTL.bit.PHSEN = 0U;
EPwm1Regs.TBCTL.bit.PHSDIR = 1U;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0U;
EPwm2Regs.CMPA.bit.CMPA = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm2Regs.CMPB.bit.CMPB = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm2Regs.CMPC = (Uint32)( 75000 / (CarrierFrequency) ) + 10UL;
EPwm2Regs.CMPD = (Uint32)( 30000 / (CarrierFrequency) ) - 1UL;
EPwm2Regs.TBPHS.bit.TBPHS = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0U; /* CMPAShadow */
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0U; /* CMPBShadow */
EPwm2Regs.CMPCTL2.bit.SHDWCMODE = 0U; /* CMPCShadow */
EPwm2Regs.CMPCTL2.bit.SHDWDMODE = 0U; /* CMPDShadow */
EPwm2Regs.TBCTL.bit.PRDLD = 0U; /* TBPRDShadow */
EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 1U; /* DBFEDShadow */
EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 1U; /* DBREDShadow */
EPwm2Regs.DBCTL.bit.HALFCYCLE = 1U;
EPwm2Regs.DBCTL.bit.IN_MODE = 0U;
EPwm2Regs.DBCTL.bit.OUT_MODE = 3U;
EPwm2Regs.DBCTL.bit.POLSEL = 2U;
EPwm2Regs.DBCTL.bit.DEDB_MODE = 0U;
EPwm2Regs.DBCTL.bit.OUTSWAP = 0U;
EPwm2Regs.TBCTL.bit.PHSEN = 0U;
EPwm2Regs.TBCTL.bit.PHSDIR = 1U;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0U;
EPwm3Regs.TBPHS.bit.TBPHS = 0U;
EPwm3Regs.CMPA.bit.CMPA = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm3Regs.CMPB.bit.CMPB = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm3Regs.CMPC = 1UL;
EPwm3Regs.CMPD = (Uint32)( 30000 / (CarrierFrequency) ) - 1UL;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0U; /* CMPAShadow */
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0U; /* CMPBShadow */
EPwm3Regs.CMPCTL2.bit.SHDWCMODE = 0U; /* CMPCShadow */
EPwm3Regs.CMPCTL2.bit.SHDWDMODE = 0U; /* CMPDShadow */
EPwm3Regs.TBCTL.bit.PRDLD = 0U; /* TBPRDShadow */
EPwm3Regs.DBCTL.bit.SHDWDBFEDMODE = 1U; /* DBFEDShadow */
EPwm3Regs.DBCTL.bit.SHDWDBREDMODE = 1U; /* DBREDShadow */
EPwm3Regs.DBCTL.bit.HALFCYCLE = 1U;
EPwm3Regs.DBCTL.bit.IN_MODE = 0U;
EPwm3Regs.DBCTL.bit.OUT_MODE = 3U;
EPwm3Regs.DBCTL.bit.POLSEL = 2U;
EPwm3Regs.DBCTL.bit.DEDB_MODE = 0U;
EPwm3Regs.DBCTL.bit.OUTSWAP = 0U;
EPwm3Regs.TBCTL.bit.PHSEN = 0U;
EPwm3Regs.TBCTL.bit.PHSDIR = 1U;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 2U;
EPwm4Regs.TBPHS.bit.TBPHS = Offset;
EPwm4Regs.CMPA.bit.CMPA = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm4Regs.CMPB.bit.CMPB = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm4Regs.CMPC = 1U;
EPwm4Regs.CMPD = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0U; /* CMPAShadow */
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0U; /* CMPBShadow */
EPwm4Regs.CMPCTL2.bit.SHDWCMODE = 0U; /* CMPCShadow */
EPwm4Regs.CMPCTL2.bit.SHDWDMODE = 0U; /* CMPDShadow */
EPwm4Regs.TBCTL.bit.PRDLD = 0U; /* TBPRDShadow */
EPwm4Regs.DBCTL.bit.SHDWDBFEDMODE = 1U; /* DBFEDShadow */
EPwm4Regs.DBCTL.bit.SHDWDBREDMODE = 1U; /* DBREDShadow */
EPwm4Regs.DBCTL.bit.HALFCYCLE = 1U;
EPwm4Regs.DBCTL.bit.IN_MODE = 0U;
EPwm4Regs.DBCTL.bit.OUT_MODE = 3U;
EPwm4Regs.DBCTL.bit.POLSEL = 2U;
EPwm4Regs.DBCTL.bit.DEDB_MODE = 0U;
EPwm4Regs.DBCTL.bit.OUTSWAP = 0U;
EPwm4Regs.TBCTL.bit.PHSEN = 0U;
EPwm4Regs.TBCTL.bit.PHSDIR = 1U;
EPwm5Regs.TBCTL.bit.SYNCOSEL = 2U;
EPwm5Regs.TBPHS.bit.TBPHS = 0U;
EPwm5Regs.CMPA.bit.CMPA = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm5Regs.CMPB.bit.CMPB = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm5Regs.CMPC = 1U;
EPwm5Regs.CMPD = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0U; /* CMPAShadow */
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0U; /* CMPBShadow */
EPwm5Regs.CMPCTL2.bit.SHDWCMODE = 0U; /* CMPCShadow */
EPwm5Regs.CMPCTL2.bit.SHDWDMODE = 0U; /* CMPDShadow */
EPwm5Regs.TBCTL.bit.PRDLD = 0U; /* TBPRDShadow */
EPwm5Regs.DBCTL.bit.SHDWDBFEDMODE = 1U; /* DBFEDShadow */
EPwm5Regs.DBCTL.bit.SHDWDBREDMODE = 1U; /* DBREDShadow */
EPwm5Regs.DBCTL.bit.HALFCYCLE = 1U;
EPwm5Regs.DBCTL.bit.IN_MODE = 0U;
EPwm5Regs.DBCTL.bit.OUT_MODE = 3U;
EPwm5Regs.DBCTL.bit.POLSEL = 2U;
EPwm5Regs.DBCTL.bit.DEDB_MODE = 0U;
EPwm5Regs.DBCTL.bit.OUTSWAP = 0U;
EPwm5Regs.TBCTL.bit.PHSEN = 0U;
EPwm5Regs.TBCTL.bit.PHSDIR = 1U;
EPwm6Regs.TBCTL.bit.SYNCOSEL = 3U;
EPwm6Regs.TBCTL2.bit.SYNCOSELX = 0U;
EPwm6Regs.TBPHS.bit.TBPHS = 0U;
EPwm6Regs.CMPA.bit.CMPA = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm6Regs.CMPB.bit.CMPB = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm6Regs.CMPC = 1U;
EPwm6Regs.CMPD = (Uint32)( 50000 / (CarrierFrequency) ) - 1UL;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0U; /* CMPAShadow */
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0U; /* CMPBShadow */
EPwm6Regs.CMPCTL2.bit.SHDWCMODE = 0U; /* CMPCShadow */
EPwm6Regs.CMPCTL2.bit.SHDWDMODE = 0U; /* CMPDShadow */
EPwm6Regs.TBCTL.bit.PRDLD = 0U; /* TBPRDShadow */
EPwm6Regs.DBCTL.bit.SHDWDBFEDMODE = 1U; /* DBFEDShadow */
EPwm6Regs.DBCTL.bit.SHDWDBREDMODE = 1U; /* DBREDShadow */
EPwm6Regs.DBCTL.bit.HALFCYCLE = 1U;
EPwm6Regs.DBCTL.bit.IN_MODE = 0U;
EPwm6Regs.DBCTL.bit.OUT_MODE = 3U;
EPwm6Regs.DBCTL.bit.POLSEL = 2U;
EPwm6Regs.DBCTL.bit.DEDB_MODE = 0U;
EPwm6Regs.DBCTL.bit.OUTSWAP = 0U;
EPwm6Regs.TBCTL.bit.PHSEN = 0U;
EPwm6Regs.TBCTL.bit.PHSDIR = 1U;
EPwm2Regs.DBRED.bit.DBRED = IntDBRED;
EPwm2Regs.DBFED.bit.DBFED = IntDBFED;
EPwm3Regs.DBRED.bit.DBRED = IntDBRED;
EPwm3Regs.DBFED.bit.DBFED = IntDBFED;
EPwm4Regs.DBRED.bit.DBRED = IntDBRED;
EPwm4Regs.DBFED.bit.DBFED = IntDBFED;
EPwm5Regs.DBRED.bit.DBRED = IntDBRED;
EPwm5Regs.DBFED.bit.DBFED = IntDBFED;
EPwm6Regs.DBRED.bit.DBRED = IntDBRED;
EPwm6Regs.DBFED.bit.DBFED = IntDBFED;
{
EALLOW;
EPwm2Regs.HRMSTEP.bit.HRMSTEP = 66;
EPwm2Regs.HRCNFG.bit.CTLMODEB = 0U;
EPwm2Regs.HRCNFG.bit.EDGMODEB = 1U;
EPwm2Regs.HRCNFG.bit.SWAPAB = 0U;
EPwm2Regs.HRCNFG.bit.AUTOCONV = 0U;
EPwm2Regs.HRCNFG.bit.SELOUTB = 0U;
EPwm2Regs.HRCNFG.bit.CTLMODE = 0U;
EPwm2Regs.HRCNFG.bit.EDGMODE = 2U;
EPwm2Regs.HRCNFG2.bit.CTLMODEDBFED = 0U;
EPwm2Regs.HRCNFG2.bit.CTLMODEDBRED = 0U;
EPwm2Regs.HRCNFG2.bit.EDGMODEDB = 3U;
EPwm2Regs.HRPWR.bit.CALPWRON = 1U;
EPwm3Regs.HRMSTEP.bit.HRMSTEP = 66;
EPwm3Regs.HRCNFG.bit.CTLMODEB = 0U;
EPwm3Regs.HRCNFG.bit.EDGMODEB = 1U;
EPwm3Regs.HRCNFG.bit.SWAPAB = 0U;
EPwm3Regs.HRCNFG.bit.AUTOCONV = 0U;
EPwm3Regs.HRCNFG.bit.SELOUTB = 0U;
EPwm3Regs.HRCNFG.bit.CTLMODE = 0U;
EPwm3Regs.HRCNFG.bit.EDGMODE = 2U;
EPwm3Regs.HRCNFG2.bit.CTLMODEDBFED = 0U;
EPwm3Regs.HRCNFG2.bit.CTLMODEDBRED = 0U;
EPwm3Regs.HRCNFG2.bit.EDGMODEDB = 3U;
EPwm3Regs.HRPWR.bit.CALPWRON = 1U;
EPwm4Regs.HRMSTEP.bit.HRMSTEP = 66;
EPwm4Regs.HRCNFG.bit.CTLMODEB = 0U;
EPwm4Regs.HRCNFG.bit.EDGMODEB = 1U;
EPwm4Regs.HRCNFG.bit.SWAPAB = 0U;
EPwm4Regs.HRCNFG.bit.AUTOCONV = 0U;
EPwm4Regs.HRCNFG.bit.SELOUTB = 0U;
EPwm4Regs.HRCNFG.bit.CTLMODE = 0U;
EPwm4Regs.HRCNFG.bit.EDGMODE = 2U;
EPwm4Regs.HRCNFG2.bit.CTLMODEDBFED = 0U;
EPwm4Regs.HRCNFG2.bit.CTLMODEDBRED = 0U;
EPwm4Regs.HRCNFG2.bit.EDGMODEDB = 3U;
EPwm4Regs.HRPWR.bit.CALPWRON = 1U;
EPwm5Regs.HRMSTEP.bit.HRMSTEP = 66;
EPwm5Regs.HRCNFG.bit.CTLMODEB = 1U;
EPwm5Regs.HRCNFG.bit.EDGMODEB = 3U;
EPwm5Regs.HRCNFG.bit.SWAPAB = 0U;
EPwm5Regs.HRCNFG.bit.AUTOCONV = 0U;
EPwm5Regs.HRCNFG.bit.SELOUTB = 0U;
EPwm5Regs.HRCNFG.bit.CTLMODE = 1U;
EPwm5Regs.HRCNFG.bit.EDGMODE = 3U;
EPwm5Regs.HRCNFG2.bit.CTLMODEDBFED = 0U;
EPwm5Regs.HRCNFG2.bit.CTLMODEDBRED = 0U;
EPwm5Regs.HRCNFG2.bit.EDGMODEDB = 3U;
EPwm5Regs.HRPWR.bit.CALPWRON = 1U;
EPwm6Regs.HRMSTEP.bit.HRMSTEP = 66;
EPwm6Regs.HRCNFG.bit.CTLMODEB = 1U;
EPwm6Regs.HRCNFG.bit.EDGMODEB = 3U;
EPwm6Regs.HRCNFG.bit.SWAPAB = 0U;
EPwm6Regs.HRCNFG.bit.AUTOCONV = 0U;
EPwm6Regs.HRCNFG.bit.SELOUTB = 0U;
EPwm6Regs.HRCNFG.bit.CTLMODE = 1U;
EPwm6Regs.HRCNFG.bit.EDGMODE = 3U;
EPwm6Regs.HRCNFG2.bit.CTLMODEDBFED = 0U;
EPwm6Regs.HRCNFG2.bit.CTLMODEDBRED = 0U;
EPwm6Regs.HRCNFG2.bit.EDGMODEDB = 3U;
EPwm6Regs.HRPWR.bit.CALPWRON = 1U;
EDIS;
}
{
EALLOW;
EPwm1Regs.TZSEL.all = 0x0000U;
EPwm1Regs.TZEINT.all = 0x0000U;
EPwm1Regs.TZCLR.all = 0x007fU;
EPwm1Regs.TZCTL.all = 0x0ff0U;
EPwm1Regs.TZCTL2.all = 0x0000U;
EPwm2Regs.TZSEL.all = 0x0000U;
EPwm2Regs.TZEINT.all = 0x0000U;
EPwm2Regs.TZCLR.all = 0x007fU;
EPwm2Regs.TZCTL.all = 0x0ff0U;
EPwm2Regs.TZCTL2.all = 0x0000U;
EPwm3Regs.TZSEL.all = 0x0000U;
EPwm3Regs.TZEINT.all = 0x0000U;
EPwm3Regs.TZCLR.all = 0x007fU;
EPwm3Regs.TZCTL.all = 0x0ff0U;
EPwm3Regs.TZCTL2.all = 0x0000U;
EPwm4Regs.TZSEL.all = 0x0000U;
EPwm4Regs.TZEINT.all = 0x0000U;
EPwm4Regs.TZCLR.all = 0x007fU;
EPwm4Regs.TZCTL.all = 0x0ff0U;
EPwm4Regs.TZCTL2.all = 0x0000U;
EPwm5Regs.TZSEL.all = 0x0000U;
EPwm5Regs.TZEINT.all = 0x0000U;
EPwm5Regs.TZCLR.all = 0x007fU;
EPwm5Regs.TZCTL.all = 0x0ff0U;
EPwm5Regs.TZCTL2.all = 0x0000U;
EPwm6Regs.TZSEL.all = 0x0000U;
EPwm6Regs.TZEINT.all = 0x0000U;
EPwm6Regs.TZCLR.all = 0x007fU;
EPwm6Regs.TZCTL.all = 0x0ff0U;
EPwm6Regs.TZCTL2.all = 0x0000U;
EDIS;
}
EPwm1Regs.ETSEL.bit.INTSEL = 4U;
EPwm1Regs.ETSEL.bit.INTSELCMP = 1U;
EPwm1Regs.ETPS.bit.INTPSSEL = 0U;
EPwm1Regs.ETPS.bit.INTPRD = 3U;
EALLOW;
PieVectTable.EPWM1_INT = Phase_Duty;
EDIS;
EPwm1Regs.ETSEL.bit.INTEN = 1U;
PieCtrlRegs.PIEIER3.all |= (1U);
IER |= 0x0004U;
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1U;
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1U;
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO9 = 1U;
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1U;
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1U;
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO4 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO4 = 1U;
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1U;
GpioCtrlRegs.GPAGMUX1.bit.GPIO5 = 0U;
GpioCtrlRegs.GPADIR.bit.GPIO5 = 1U;
GCNT0 = EPwm2Regs.GLDCTL.bit.GLDCNT;
EPwm1Regs.TBCTL.bit.CTRMODE = 0U;
EPwm2Regs.TBCTL.bit.CTRMODE = 0U;
EPwm3Regs.TBCTL.bit.CTRMODE = 0U;
EPwm4Regs.TBCTL.bit.CTRMODE = 0U;
EPwm5Regs.TBCTL.bit.CTRMODE = 0U;
EPwm6Regs.TBCTL.bit.CTRMODE = 0U;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0x1U;
EDIS;
ret = 0U;
}
return ret;
}
void InitSystem(void)
{
DisableDog();
MemCopy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize);//
InitFlash_Bank0();
InitFlash_Bank1();
// *IMPORTANT*
// The Device_cal function, which copies the ADC & oscillator calibration values
// from TI reserved OTP into the appropriate trim registers, occurs automatically
// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC and oscillators to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
EALLOW;
//enable pull-ups on unbonded IOs as soon as possible to reduce power consumption.
// GPIO_EnableUnbondedIOPullups();
CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
CpuSysRegs.PCLKCR13.bit.ADC_C = 1;
CpuSysRegs.PCLKCR13.bit.ADC_D = 1;
//check if device is trimmed
if(*((Uint16 *)0x5D1B6) == 0x0000){
//device is not trimmed, apply static calibration values
AnalogSubsysRegs.ANAREFTRIMA.all = 31709;
AnalogSubsysRegs.ANAREFTRIMB.all = 31709;
AnalogSubsysRegs.ANAREFTRIMC.all = 31709;
AnalogSubsysRegs.ANAREFTRIMD.all = 31709;
}
CpuSysRegs.PCLKCR13.bit.ADC_A = 0;
CpuSysRegs.PCLKCR13.bit.ADC_B = 0;
CpuSysRegs.PCLKCR13.bit.ADC_C = 0;
CpuSysRegs.PCLKCR13.bit.ADC_D = 0;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2; /* 1/4 = 50MHz */
InitSysPll(XTAL_OSC,IMULT_20,FMULT_0,PLLCLK_BY_2); //PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV)
EDIS;
//Turn on all peripherals
InitPeripheralClocks();
ClkCfgRegs.PERCLKDIVSEL.all = 0x00000051; /* EMIF1, EMIF2, EPWM : 1/2 = 100MHz */
ClkCfgRegs.CLKSRCCTL3.bit.XCLKOUTSEL = 2; /* source of XCLKOUT = CPU1.SYSCLK */
ClkCfgRegs.XCLKOUTDIVSEL.bit.XCLKOUTDIV = 2;
EALLOW;
//
// Initialize and wait for CLA1ToCPUMsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
//
// Initialize and wait for CPUToCLA1MsgRAM
//
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
EDIS;
// Step 2. Initialize GPIO:
// This example function is found in the F2837xS_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
InitGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.
InitPieVectTable();
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// GPIOInit();
}
#pragma INTERRUPT(ISR_ILLEGAL)
static void ISR_ILLEGAL(void)
{
IER = 0x0000; // Disable CPU interrupts
IFR = 0x0000; // Clear all CPU interrupt flags
InitGpio();
InitPieCtrl();
InitPieVectTable();
InitPeripheralClocks();
__enable_interrupts();
for(;;){}
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
// asm(" ESTOP0");
// for(;;);
}
//---------------------------------------------------------------------------
// Example: InitFlash_Bank1
//---------------------------------------------------------------------------
// This function initializes the Flash Control registers for Bank1
static void InitFlash_Bank0(void)
{
EALLOW;
// set VREADST to the proper value for the
// flash banks to power up properly
// This sets the bank power up delay
Flash0CtrlRegs.FBAC.bit.VREADST = 0x14;
//At reset bank and pump are in sleep
//A Flash access will power up the bank and pump automatically
//After a Flash access, bank and pump go to low power mode (configurable in FBFALLBACK/FPAC1 registers)-
//if there is no further access to flash
//Power up Flash bank and pump and this also sets the fall back mode of flash and pump as active
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
//Disable Cache and prefetch mechanism before changing wait states
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
//Set waitstates according to frequency
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
// #if CPU_FRQ_200MHZ
// Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
// #endif
//
// #if CPU_FRQ_150MHZ
// Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
// #endif
//
// #if CPU_FRQ_120MHZ
// Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
// #endif
Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
//Enable Cache and prefetch mechanism to improve performance
//of code executed from Flash.
Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
//At reset, ECC is enabled
//If it is disabled by application software and if application again wants to enable ECC
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
__asm(" RPT #7 || NOP");
}
//---------------------------------------------------------------------------
// Example: InitFlash_Bank1
//---------------------------------------------------------------------------
// This function initializes the Flash Control registers for Bank1
static void InitFlash_Bank1(void)
{
EALLOW;
// set VREADST to the proper value for the
// flash banks to power up properly
// This sets the bank power up delay
Flash1CtrlRegs.FBAC.bit.VREADST = 0x14;
//At reset bank and pump are in sleep
//A Flash access will power up the bank and pump automatically
//After a Flash access, bank and pump go to low power mode (configurable in FBFALLBACK/FPAC1 registers)-
//if there is no further access to flash
//Power up Flash bank and pump and this also sets the fall back mode of flash and pump as active
Flash1CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
Flash1CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
//Disable Cache and prefetch mechanism before changing wait states
Flash1CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
Flash1CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;
//Set waitstates according to frequency
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
// #if CPU_FRQ_200MHZ
Flash1CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;
// #endif
// #if CPU_FRQ_150MHZ
// Flash1CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
// #endif
// #if CPU_FRQ_120MHZ
// Flash1CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;
// #endif
//Enable Cache and prefetch mechanism to improve performance
//of code executed from Flash.
Flash1CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
Flash1CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;
//At reset, ECC is enabled
//If it is disabled by application software and if application again wants to enable ECC
Flash1EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
__asm(" RPT #7 || NOP");
}
//---------------------------------------------------------------------------
// Example: InitPll:
//---------------------------------------------------------------------------
// This function initializes the PLL registers.
//
// Note: The internal oscillator CANNOT be used as the PLL source if the
// PLLSYSCLK is configured to frequencies above 194 MHz.
static void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel)
{
if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) &&
(imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) &&
(fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) &&
(divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
{
//everything is set as required, so just return
return;
}
if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)
{
switch (clock_source)
{
case INT_OSC1:
SysIntOsc1Sel();
break;
case INT_OSC2:
SysIntOsc2Sel();
break;
case XTAL_OSC:
SysXtalOscSel();
break;
}
}
EALLOW;
// first modify the PLL multipliers
if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT)
{
// Bypass PLL and set dividers to /1
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0;
// Program PLL multipliers
Uint32 temp_syspllmult = ClkCfgRegs.SYSPLLMULT.all;
ClkCfgRegs.SYSPLLMULT.all = ((temp_syspllmult & ~(0x37FU)) |
((fmult << 8U) | imult));
ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; // Enable SYSPLL
// Wait for the SYSPLL lock
while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
// Write a multiplier again to ensure proper PLL initialization
// This will force the PLL to lock a second time
ClkCfgRegs.SYSPLLMULT.bit.IMULT = imult; // Setting integer multiplier
// Wait for the SYSPLL re-lock
while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
}
// Set divider to produce slower output frequency to limit current increase
if(divsel != PLLCLK_BY_126)
{
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1;
}else
{
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
}
// Enable PLLSYSCLK is fed from system PLL clock
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
// Small 100 cycle delay
asm(" RPT #100 || NOP");
// Set the divider to user value
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
EDIS;
}
//---------------------------------------------------------------------------
// Example: SysIntOsc1Sel:
//---------------------------------------------------------------------------
// This function switches to Internal Oscillator 1 and turns off all other clock
// sources to minimize power consumption
static void SysIntOsc1Sel (void) {
EALLOW;
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1
EDIS;
}
//---------------------------------------------------------------------------
// Example: SysIntOsc2Sel:
//---------------------------------------------------------------------------
// This function switches to Internal oscillator 2 from External Oscillator
// and turns off all other clock sources to minimize power consumption
// NOTE: If there is no external clock connection, when switching from
// INTOSC1 to INTOSC2, EXTOSC and XLCKIN must be turned OFF prior
// to switching to internal oscillator 1
static void SysIntOsc2Sel (void) {
EALLOW;
ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2
EDIS;
}
//---------------------------------------------------------------------------
// Example: SysXtalOscSel:
//---------------------------------------------------------------------------
// This function switches to External CRYSTAL oscillator and turns off all other clock
// sources to minimize power consumption. This option may not be available on all
// device packages
static void SysXtalOscSel (void) {
EALLOW;
ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL
EDIS;
}
//---------------------------------------------------------------------------
// InitPeripheralClocks
//---------------------------------------------------------------------------
// This function initializes the clocks for the peripherals.
//
// Note: In order to reduce power consumption, turn off the clocks to any
// peripheral that is not specified for your part-number or is not used in the
// application
static void InitPeripheralClocks()
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
CpuSysRegs.PCLKCR0.bit.DMA = 1;
CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1;
CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1;
CpuSysRegs.PCLKCR0.bit.HRPWM = 0;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
CpuSysRegs.PCLKCR1.bit.EMIF1 = 0;
CpuSysRegs.PCLKCR1.bit.EMIF2 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM1 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM4 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM5 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM6 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM7 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM8 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM9 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM10 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM11 = 0;
CpuSysRegs.PCLKCR2.bit.EPWM12 = 0;
CpuSysRegs.PCLKCR3.bit.ECAP1 = 0;
CpuSysRegs.PCLKCR3.bit.ECAP2 = 0;
CpuSysRegs.PCLKCR3.bit.ECAP3 = 0;
CpuSysRegs.PCLKCR3.bit.ECAP4 = 0;
CpuSysRegs.PCLKCR3.bit.ECAP5 = 0;
CpuSysRegs.PCLKCR3.bit.ECAP6 = 0;
CpuSysRegs.PCLKCR4.bit.EQEP1 = 0;
CpuSysRegs.PCLKCR4.bit.EQEP2 = 0;
CpuSysRegs.PCLKCR4.bit.EQEP3 = 0;
CpuSysRegs.PCLKCR6.bit.SD1 = 0;
CpuSysRegs.PCLKCR6.bit.SD2 = 0;
CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
CpuSysRegs.PCLKCR7.bit.SCI_B = 0;
CpuSysRegs.PCLKCR7.bit.SCI_C = 0;
CpuSysRegs.PCLKCR7.bit.SCI_D = 0;
CpuSysRegs.PCLKCR8.bit.SPI_A = 0;
CpuSysRegs.PCLKCR8.bit.SPI_B = 0;
CpuSysRegs.PCLKCR8.bit.SPI_C = 0;
CpuSysRegs.PCLKCR9.bit.I2C_A = 0;
CpuSysRegs.PCLKCR9.bit.I2C_B = 0;
CpuSysRegs.PCLKCR10.bit.CAN_A = 0;
CpuSysRegs.PCLKCR10.bit.CAN_B = 0;
CpuSysRegs.PCLKCR11.bit.McBSP_A = 0;
CpuSysRegs.PCLKCR11.bit.McBSP_B = 0;
CpuSysRegs.PCLKCR11.bit.USB_A = 0;
CpuSysRegs.PCLKCR12.bit.uPP_A = 0;
CpuSysRegs.PCLKCR13.bit.ADC_A = 0;
CpuSysRegs.PCLKCR13.bit.ADC_B = 0;
CpuSysRegs.PCLKCR13.bit.ADC_C = 0;
CpuSysRegs.PCLKCR13.bit.ADC_D = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS1 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS2 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS3 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS4 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS5 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS6 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS7 = 0;
CpuSysRegs.PCLKCR14.bit.CMPSS8 = 0;
CpuSysRegs.PCLKCR16.bit.DAC_A = 0;
CpuSysRegs.PCLKCR16.bit.DAC_B = 0;
CpuSysRegs.PCLKCR16.bit.DAC_C = 0;
EDIS;
}
//Low-level functions for GPIO configuration
//Sets all pins to be muxed to GPIO in input mode with pull-ups enabled.
//Also disables open drain and polarity inversion and sets the qualification
//to synchronous. Also unlocks all GPIOs
static void InitGpio()
{
volatile Uint32 *gpioBaseAddr;
Uint16 regOffset;
//Disable pin locks
EALLOW;
GpioCtrlRegs.GPALOCK.all = 0x00000000;
GpioCtrlRegs.GPBLOCK.all = 0x00000000;
GpioCtrlRegs.GPCLOCK.all = 0x00000000;
GpioCtrlRegs.GPDLOCK.all = 0x00000000;
GpioCtrlRegs.GPELOCK.all = 0x00000000;
GpioCtrlRegs.GPFLOCK.all = 0x00000000;
//Fill all registers with zeros. Writing to each register separately
//for six GPIO modules would make this function *very* long. Fortunately,
//we'd be writing them all with zeros anyway, so this saves a lot of space.//あとで
gpioBaseAddr = (Uint32 *)&GpioCtrlRegs;
for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++)
{
//Hack to avoid enabling pull-ups on all pins. GPyPUD is offset
//0x0C in each register group of 0x40 words. Since this is a
//32-bit pointer, the addresses must be divided by 2.
if (regOffset % (0x40/2) != (0x0C/2))
gpioBaseAddr[regOffset] = 0x00000000;
}
gpioBaseAddr = (Uint32 *)&GpioDataRegs;
for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++)
{
gpioBaseAddr[regOffset] = 0x00000000;
}
EDIS;
}
//---------------------------------------------------------------------------
// InitPieCtrl:
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
static void InitPieCtrl(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
}
static void InitPieVectTable(void)
{
int16 i;
Uint32 Source = (Uint32)ISR_ILLEGAL;
Uint32 *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 224; i++)
*Dest++ = Source;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
//---------------------------------------------------------------------------
// Example: DisableDog:
//---------------------------------------------------------------------------
// This function disables the watchdog timer.
static void DisableDog(void)
{
volatile Uint16 temp;
EALLOW;
//Grab the clock config so we don't clobber it
temp = WdRegs.WDCR.all & 0x0007;
WdRegs.WDCR.all = 0x0068 | temp;
EDIS;
}
// This function will copy the specified memory contents from
// one location to another.
//
// Uint16 *SourceAddr Pointer to the first word to be moved
// SourceAddr < SourceEndAddr
// Uint16* SourceEndAddr Pointer to the last word to be moved
// Uint16* DestAddr Pointer to the first destination word
//
// No checks are made for invalid memory locations or that the
// end address is > then the first start address.
static void MemCopy(Uint16* DestAddr, Uint16* SourceAddr, Uint32 size )
{
while(size!=0)
{
*DestAddr++ = *SourceAddr++;
size--;
}
return;
}
//===========================================================================
// End of file.
//===========================================================================
Then,ePWM2's GLDCNT and ePWM3's GLDCNT changes in the same way.
EPWM2 always reloads registers when GLDCNT changes 2 to 0.
But EPWM3 reloads registers when GLDCNT 2 to 0 at first,GLDCNT changes 1 to 2 at second and subsequent
This image was captured when the first pulse of ePWM1 occured.
Please tell me and Thank you for your patience with my poor English.