Part Number: LAUNCHXL-F28377S
Tool/software: Code Composer Studio
Good evening,
We are writing to you, because we have a problem, on the launchpad already mentioned.
The thing is that, we need to program 8 PWM (pwm7A,B pwm8A,B pwm9A,B pwm10A,B) and we decided that the sync pwm will be pwm7.
pwm8, pwm9 and pwm10 have to be on phase with pwm7, the problem is that pwm10 wont sync with 7. we attached the code.
Thanks
Code:
void Setup_ePWM1(void)
{
EPwm7Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 2
EPwm7Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm7Regs.AQCTLA.bit.CAU =1; // set ePWM1A on CMPA up
EPwm7Regs.AQCTLA.bit.CAD =2;
EPwm7Regs.AQCTLB.bit.CBU =1; // set ePWM1A on CMPA up
EPwm7Regs.AQCTLB.bit.CBD =2;
// clear ePWM1A on CMPA down
EPwm7Regs.TBPRD = tope; //
EPwm7Regs.CMPA.bit.CMPA = 0.5*tope; // 50% duty cycle first
EPwm7Regs.CMPB.bit.CMPB = 0.5*tope;
EPwm7Regs.TBCTL.bit.SYNCOSEL = 1;
EPwm8Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm8Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 2
EPwm8Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm8Regs.AQCTLA.bit.CAU =1; // set ePWM1A on CMPA up
EPwm8Regs.AQCTLA.bit.CAD =2;
EPwm8Regs.AQCTLB.bit.CBU =1; // set ePWM1A on CMPA up
EPwm8Regs.AQCTLB.bit.CBD =2;
// clear ePWM1A on CMPA down
EPwm8Regs.TBPRD = tope; //
EPwm8Regs.CMPA.bit.CMPA = 0.5*tope; // 50% duty cycle first
EPwm8Regs.CMPB.bit.CMPB = 0.5*tope;
EPwm8Regs.TBCTL.bit.PHSEN = 1;
EPwm8Regs.TBPHS.bit.TBPHS = 0;
// EPwm8Regs.TBCTL.bit.SYNCOSEL = 0;// enable phase shift for ePWM3
EPwm9Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm9Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 2
EPwm9Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm9Regs.AQCTLA.bit.CAU =1; // set ePWM1A on CMPA up
EPwm9Regs.AQCTLA.bit.CAD =2;
EPwm9Regs.AQCTLB.bit.CBU =1; // set ePWM1A on CMPA up
EPwm9Regs.AQCTLB.bit.CBD =2;
// clear ePWM1A on CMPA down
EPwm9Regs.TBPRD = tope; //
EPwm9Regs.CMPA.bit.CMPA = 0.5*tope; // 50% duty cycle first
EPwm9Regs.CMPB.bit.CMPB = 0.5*tope;
EPwm9Regs.TBCTL.bit.PHSEN = 1;
EPwm9Regs.TBPHS.bit.TBPHS = 0;
//EPwm9Regs.TBCTL.bit.SYNCOSEL = 0;// enable phase shift for ePWM3
EPwm7Regs.TBCTL.bit.SYNCOSEL = 1;
SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN=2;
EPwm10Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1
EPwm10Regs.TBCTL.bit.HSPCLKDIV = 0; // HSPCLKDIV = 2
EPwm10Regs.TBCTL.bit.CTRMODE = 2; // up - down mode
EPwm10Regs.AQCTLA.bit.CAU =1; // set ePWM1A on CMPA up
EPwm10Regs.AQCTLA.bit.CAD =2;
EPwm10Regs.AQCTLB.bit.CBU =1; // set ePWM1A on CMPA up
EPwm10Regs.AQCTLB.bit.CBD =2;
// clear ePWM1A on CMPA down
EPwm10Regs.TBPRD = tope; //
EPwm10Regs.CMPA.bit.CMPA = 0.5*tope; // 50% duty cycle first
EPwm10Regs.CMPB.bit.CMPB = 0.5*tope;
EPwm10Regs.TBSTS.bit.SYNCI=1;
EPwm10Regs.TBCTL.bit.SYNCOSEL = 0;
EPwm10Regs.TBCTL.bit.PHSEN = 1;
EPwm10Regs.TBPHS.bit.TBPHS = 0;
}