ISR never accessed

Janina Sanchez53834

Other Parts Discussed in Thread: TMS320F28335

Hey everyone,

I am making a Tranmission form CAN A to CAN B program with TMS320F28335, where im transmiting from mailbox9 CANA to maiblox9 CANB. The transmission worked properly but then when i tried ti implement the interrupts for the mailboxes, the ISR function is never accessed. I have put a counter in each function and they both remain in zero while the programm is running so the ISR is never called. I have configured everything as the manual specifies and i dont know why the interrupts are not working. Please if you have any suggestions they re very welcomed

This is my Code

/***********************************************************************/

/*Transmission from CAN A to CAN B with the implementation of interrupts*/

/***********************************************************************/

#include "DSP28x_Project.h" // headerfiles

#define TCount 100000 // Number of transmissions

interrupt void Can_Tx_ISR(void);
interrupt void Can_Rx_ISR(void);

struct ECAN_REGS ECanaShadow;
struct ECAN_REGS ECanbShadow;

Uint16 int0count = 0; // Counter to track the # of level 0 interrupts
Uint16 int1count = 0; // Counter to track the # of level 1 interrupts

void main ()
{

Uint16 i;
Uint16 MessageCount;

// Initialize the System

        InitSysCtrl();

//Initialize GPIO for eCan

        InitECanGpio();

//Pie Control Registers are initialized to their default state

        InitPieCtrl();

// Enable CPU interrupts and clear all CPU interrupt flags:
   //IER |= M_INT9; //Group 9, CAN Interrupts

           EnableInterrupts();

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).

        InitPieVectTable();

// Initialize CAN A and CAN B

        InitECan();

// Initialize PIE vector table and clear all interrupts

        DINT;
        IER = 0x0000; //Dissable CPU interrupts
        IFR = 0x0000; //Clear Flags

// Initialize Pie Control Registers To Default State

        InitPieCtrl();

        DINT;

//Beginning of CAN configuration

// Setting the mailboxes
// Transmission CAN A-MBOX 9

    ECanaShadow.CANTRR.all=ECanaRegs.CANTRR.all;
    ECanaShadow.CANTRR.bit.TRR9= 1;
    ECanaRegs.CANTRR.all=ECanaShadow.CANTRR.all;

do {

ECanaShadow.CANTRS.all=ECanaRegs.CANTRS.all;
}
    while( ECanaShadow.CANTRS.bit.TRS9 != 0); //Wait for TRS9 to be cleared

//Dissable Mailboxes

    //CAN A

        ECanaShadow.CANME.all=ECanaRegs.CANME.all;
        ECanaShadow.CANME.bit.ME9=0;              // Dissable the Mailbox
        ECanaRegs.CANME.all=ECanaShadow.CANME.all;

    //CAN B

        ECanbShadow.CANME.all=ECanbRegs.CANME.all;
        ECanbShadow.CANME.bit.ME9=0;
        ECanbRegs.CANME.all=ECanbShadow.CANME.all;

// Load Message Identifiers

    //CAN A
        ECanaMboxes.MBOX9.MSGID.all=0x15AC0000;
        ECanaMboxes.MBOX9.MSGID.bit.AME=0;
        ECanaMboxes.MBOX9.MSGID.bit.AAM=0;

    //CAN B
        ECanbMboxes.MBOX9.MSGID.all=0x15AC0000;

// Write to DLC field in Message Control reg

    //CAN A
        ECanaMboxes.MBOX9.MSGCTRL.bit.DLC= 8;

    //CAN B
        ECanbMboxes.MBOX9.MSGCTRL.bit.DLC= 8;

//Enable Mailboxes

    //CAN A

        ECanaShadow.CANME.all=ECanaRegs.CANME.all;
        ECanaShadow.CANME.bit.ME9=1;              // Enable Mailbox
        ECanaRegs.CANME.all=ECanaShadow.CANME.all;

    //CAN B

        ECanbShadow.CANME.all=ECanbRegs.CANME.all;
        ECanbShadow.CANME.bit.ME9=1;
        ECanbRegs.CANME.all=ECanbShadow.CANME.all;

//Set the Mailbox CAN A for Transmission and CAN B for reception

    // CAN A

        ECanaShadow.CANMD.all=ECanaRegs.CANMD.all;
        ECanaShadow.CANMD.bit.MD9=0;              // Set Mailbox direction to Transmit
        ECanaRegs.CANMD.all=ECanaShadow.CANMD.all;

    //CAN B

        ECanbShadow.CANMD.all=ECanbRegs.CANMD.all;
        ECanbShadow.CANMD.bit.MD9=1;              // Set Mailbox direction to Receive
        ECanbRegs.CANMD.all=ECanbShadow.CANMD.all;

//Write the Message Data into the Mailbox Data Field

        ECanaMboxes.MBOX9.MDL.all= 0xAAAABBBB;
        ECanaMboxes.MBOX9.MDH.all= 0x00000000;

/*----------------------------------------------------------------------------------------------------------*/
//---------------------------------- Enabling The Interrupts------------------------------------------------//

//Configuring Interrupt Handling

        ECanaShadow.CANMIL.all=0xFFFFFFFF;              //Sets Mailbox Interrupts to level 1
        //ECanaShadow.CANMIL.all=0x00000000;            //Sets Mailbox Interrupts to level 0
        ECanaRegs.CANMIL.all= ECanaShadow.CANMIL.all;


        ECanbShadow.CANMIL.all=0xFFFFFFFF;                //Sets Mailbox Interrupts to level 1
        //ECanbShadow.CANMIL.all=0x00000000;                //Sets Mailbox Interrupts to level 0
        ECanbRegs.CANMIL.all= ECanbShadow.CANMIL.all;


        ECanaShadow.CANMIM.all=ECanaRegs.CANMIM.all;
        ECanaShadow.CANMIM.bit.MIM9=1;
        ECanaRegs.CANMIM.all= ECanaShadow.CANMIM.all;

        ECanbShadow.CANMIM.all=ECanbRegs.CANMIM.all;
        ECanbShadow.CANMIM.bit.MIM9=1;
        ECanbRegs.CANMIM.all= ECanbShadow.CANMIM.all;
        //ECanbRegs.CANMIM.all =0xFFFFFFFF;

//Configuring the CANGIM register

        ECanaShadow.CANGIM.all=ECanaRegs.CANGIM.all;
        ECanaShadow.CANGIM.bit.AAIM=1;
        ECanaShadow.CANGIM.bit.WDIM=1;
        ECanaShadow.CANGIM.bit.WUIM=1;
        ECanaShadow.CANGIM.bit.BOIM=1;
        ECanaShadow.CANGIM.bit.EPIM=1;
        ECanaShadow.CANGIM.bit.WLIM=1;
        ECanaShadow.CANGIM.bit.I1EN=1;
    //    ECanaShadow.CANGIM.bit.I0EN=1;
        ECanaShadow.CANGIM.bit.GIL=1;
        ECanaRegs.CANGIM.all=ECanaShadow.CANGIM.all;

        ECanbShadow.CANGIM.all=ECanbRegs.CANGIM.all;
        ECanbShadow.CANGIM.bit.AAIM=1;
        ECanbShadow.CANGIM.bit.WDIM=1;
        ECanbShadow.CANGIM.bit.WUIM=1;
        ECanbShadow.CANGIM.bit.BOIM=1;
        ECanbShadow.CANGIM.bit.EPIM=1;
        ECanbShadow.CANGIM.bit.WLIM=1;
        ECanbShadow.CANGIM.bit.I1EN=1;
    //    ECanbShadow.CANGIM.bit.I0EN=1;
        ECanbShadow.CANGIM.bit.GIL=1;
        ECanbRegs.CANGIM.all=ECanbShadow.CANGIM.all;

// Adress the Peripheral vector to the ISR routine function found in this file

    EALLOW;
    PieVectTable.ECAN1INTA= &Can_Tx_ISR;
    PieVectTable.ECAN1INTB= &Can_Rx_ISR;
    EDIS;

// Enable interrupts required for this example

    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   //Enable the PIE block
    PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables the PIE to drive a pulse into the CPU

    PieCtrlRegs.PIEIER9.bit.INTx6 = 1;   //Enable INT5
    PieCtrlRegs.PIEIFR9.bit.INTx8 = 1;   //Enable INT7
    IER|=0x0100;                         // Enable CPU INT
    EINT;                                // Enable Global Interrupts

/*-----------------------------------------------------------------------------------------------------------------*/
/*-------------------------------------Begin Transmission----------------------------------------------------------*/

for(i=0; i<TCount; i++){

    //MBOX 9 from Can A Transmitting

        ECanaShadow.CANTRS.all=ECanaRegs.CANTRS.all;
        ECanaShadow.CANTRS.bit.TRS9=1;
        ECanaRegs.CANTRS.all=ECanaShadow.CANTRS.all;


    do {

         ECanaShadow.CANTA.all= ECanaRegs.CANTA.all;

}        while(ECanaShadow.CANTA.bit.TA9 == 0); // wait for TA9 to be set

//Clear the TA for next transmission

    /*    ECanaShadow.CANTA.all= ECanaRegs.CANTA.all;
         ECanaShadow.CANTA.bit.TA9= 0;
         ECanaRegs.CANTA.all=ECanaShadow.CANTA.all;*/

         ECanaMboxes.MBOX9.MDH.all++;
        MessageCount++;
}

}

/*-----------------------------------------------------------------------------------------------------------------------*/
/*------------------------------------------ISR Functions----------------------------------------------------------------*/

interrupt void Can_Tx_ISR(void)
{
//Clear TA bit to Clear the GMFIn bit

        ECanaShadow.CANTA.all= ECanaRegs.CANTA.all;
        ECanaShadow.CANTA.bit.TA9=0;
        ECanaRegs.CANTA.all=ECanaShadow.CANTA.all;


int0count++; // Interrupt counter

// Re-enable core interrupts and CAN int from PIE module

        PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
        IER |= 0x0100; // Enable INT9
        EINT;
         return;
}

interrupt void Can_Rx_ISR(void)
{
//Clear RMP bit to clear the GMIFn bit

        ECanbShadow.CANRMP.all=ECanbRegs.CANRMP.all;
        ECanbShadow.CANRMP.bit.RMP9=0;
        ECanbRegs.CANRMP.all=ECanbShadow.CANRMP.all;

int1count++; // Interrupt counter

// Re-enable core interrupts and CAN int from PIE module

        PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
         IER |= 0x0100; // Enable INT9
         EINT;
         return;

}

over 15 years ago

0 Lori Heustess over 15 years ago

TI__Guru* 93800 points

Janina Sanchez said:
PieCtrlRegs.PIEIFR9.bit.INTx8 = 1; //Enable INT7

Janina,

Perhaps a place to start - I think there is a typo in the above - should it be the enable PIEIER9 (not the flag - PIEIFR9)

-Lori

0 Janina Sanchez53834 over 15 years ago in reply to Lori Heustess

Prodigy 60 points

Thanks Lori didnt notice it, I changed it. Still only the Transmit ISR gets accessed the Receive one remains not being accessed at all.

Janina

0 Frank Bormann over 15 years ago in reply to Janina Sanchez53834

Mastermind 7585 points

Janina,

your code misses some interrupt enable steps. Where do you write the addresses of your interrupt service routines into the PIE - vector table? Also, I could not find an instruction to enable the PIE - lines PIEIER9.ibt.INTx5 or INTx6 (depending which CAN interrupt level ECAN1 or ECAN0 you use).

Regards

0 Frank Bormann over 15 years ago in reply to Frank Bormann

Mastermind 7585 points

Janina,

sorry, just disregard my previous email, after a 2nd inspection of your code I found the missing setups.

0 Janina Sanchez53834 over 15 years ago in reply to Frank Bormann

Prodigy 60 points

Well i ve made some changes in the code and basically whats going on right now is that the receive ISR is never accesed while the transmit one works completely fine. I would assume that its because the message is not being receive properly by the enables MBOX 9 , my question is what can be the cause of this?

0 Lori Heustess over 15 years ago in reply to Janina Sanchez53834

TI__Guru* 93800 points

Janina Sanchez said:
Well i ve made some changes in the code and basically whats going on right now is that the receive ISR is never accesed while the transmit one works completely fine. I would assume that its because the message is not being receive properly by the enables MBOX 9 , my question is what can be the cause of this?

Janina,

I was going to suggest a hardware connection issue, but if I understand the test works when polling is used but does not work when interrupts are used (is that correct?). I would suggest checking various flags to see possibly where things went wrong.

-Lori

C2000™︎ microcontrollers

C2000 microcontrollers forum

ISR never accessed