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TMS320C28346: Confirm C28346 boot via McBSP

Kaka
Guru 24520 points
Part Number: TMS320C28346

Hi TI Experts,

Please let me confirm the following question.

Now customer will use the C28346 and F28375S devices for their application. And they are considering that C28346 will be boot up from F28375S via McBSP. According to the document which is Bootloader feature(sprufn5b.pdf), it is described about "Bit-Rate Values for Different XCLKIN Values" on table7. So they have some questions as below.

[Question]
Does F28375S need to sent those bit rate to C28346 device? Or can F28375S use more higher bit rate because this value is only the send value from C28346?

If you have any questions, please let me know.
Best regards.
Kaka

  • 0
    Guru 30330 points
    Kaka,

    I am not quite sure I understand your question. You are asking if you can give the C28346 a faster bit rate for boot? It looks to me like the bit rate can be higher if you provide either a faster XCLKIN or load a custom kernel to change the clock settings of the MCBSP before continuing to download remaining data. By SYSCLK is 1/2 of XCLKIN, LSPCLK is 1/4 of SYSCLK, and the CLKG is 1/2 LSPCLK. If you fed 60MHz to XCLKIN, the resulting CLKG would be 3.75MHz.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Guru 24520 points

    Hi Mark.

    Thank you for your comments.
    Yes, the external device(F28375 in my customer case) provide a faster bit rate to C28346 during boot.
    Please let me confirm the following simple question.
    [Question]
    When C28346 will boot via McBSP, does the McBSP of C28346 work as master?
    i.e.Will C28346 provide the clock to F28375 during boot?

    Best regards.
    Kaka

  • 0 in reply to Kaka
    Guru 30330 points
    Kaka,

    The McBSP on the C2834x is in Slave Mode. It is expecting to see a clock on MCLKX in order to receive and transmit the data. This is documented explicitly in section 2.15 of SPRUFN5B. As I mentioned previously, if the customer would like a faster bit rate, they can either provide faster CLKIN to C2834x, have an initial boot kernel to adjust the SYSCLK and McBSP clock settings, or do a combination of both.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Guru 24520 points
    Hi Mark,

    Thank you for your kind comments.
    Please let me confirm the following one more question.
    To summary your comments, customer need to satisfied with the Bit-Rate Values for Different XCLKIN Values" on table7 if not using the custom boot loader. And they can be the higher bit rate with using customer bootloader before downloading the data. Is my understand correct?

    And would you please teach me the maximum bit rate without using the custom bootloader(i.e Use ROM Bootloader) when used the XCLKIN to 60MHz ?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    Hi Mark,

    Would you please provide your comment for my question?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 30330 points

    Kaka said:
    To summary your comments, customer need to satisfied with the Bit-Rate Values for Different XCLKIN Values" on table7 if not using the custom boot loader. And they can be the higher bit rate with using customer bootloader before downloading the data. Is my understand correct?

    Yes. If using the standard boot loader, the Master McBSP must provide the bit clock to C28346 based on the frequency prescribed by the table. They can write a custom boot loader to increase the frequency. 

    Kaka said:
    And would you please teach me the maximum bit rate without using the custom bootloader(i.e Use ROM Bootloader) when used the XCLKIN to 60MHz ?
     

    You can extrapolate the frequency by using the provided values in the table. if you double XCLKIN, CLKG will double. So for 60 MHz XCLKIN, the CLKG will be 3.75 MHz.

    Thanks,
    Mark

  • 0 in reply to Mark Labbato
    Guru 24520 points

    Hi Mark,

    Thank you for your comments.
    Please let me confirm the following question...
    If customer used the 20MHz for C28346, must host CPUI(F28375 in this case) send the clock of meeting the speed specification on table7?
    i.e. SYSCLKOUT = 10MHz, LSPCLK = 2.5MHz, CLKG= 1.25MHz.

    Is my understanding correct?

    Best regards.
    Kaka

  • 0 in reply to Kaka
    Guru 30330 points
    Yes. That is correct.
  • 0 in reply to Mark Labbato
    Guru 24520 points
    Hi

    Thank you for your comment. I got it.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points

    Hi Mark,

    I got more question my customer. Please let me confirm this.
    They thought if F28375S send the faster data than table7, C28346 could receive/transmit the data because the McBSP is synchronized with FCYNC and MCLK.
    So, they would like to know why the output clock of F28375S need to adjust with the input clock which is used on C28346.

    Best regards.
    Kaka

  • 0 in reply to Kaka
    Guru 24520 points
    Hi Mark,

    I am waiting for your kind feedback now...

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 30330 points

    Kaka,

    The McBSP Timing Requirements in the Datasheet (Table 6-49 of SPRS516) state that this is not possible. The maximum clock rate that the McBSP can transmit or receive is equal to the CLKG setting. As CLKG is configured to be LSPCLK/2, the input clock is limited to that frequency. 

    -Mark

  • 0 in reply to Mark Labbato
    Guru 24520 points
    Hi Mark,

    Thank you for your kind answer.
    I got it. I will explain this to my customer.

    Best regards.
    Kaka