Dear Experts,
Some time ago I had an issue with the TMS320F28075 I2C peripheral in slave mode transmitter. During sustained transfers, the I2C peripheral hangs stretching the SCL line indefinitely. I see that code has pushed a new data in the transmit register but the data doesn’t come out and SCL is kept LOW. I2C is operating in non-FIFO mode, and I’m wondering if in some cases there is the chance to get a transmit buffer overrun event.
There seems to be relevant register, I2CEMDR. Register contains BC-bit for backwards compatibility mode. According to TRM, "bit affects the timing of the transmit status bits in the I2CSTR register when in slave transmitter mode.". In table 19-21, TRM refers to Figure 9-17 for more details, but it seems there is a mistake in TRM since figure 9-17 is not relating to this matter. When BC-bit is changed to zero, bus works just fine. Is there any explanation for backwards compatibility mode and BC-bit?
Thanks!
With best regards,
Juha
