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TMS320F28377D: TMS320F28377D many caps on VDDs needed ?

Part Number: TMS320F28377D

Hi,

customer will develop a 8-layer PCB for F28377D Delfino in QFP174 package.

He will use separate PCB layers for GND and for 3.3V.

By looking into DS, we found that approx 20 VDDIO pins needs a separate dedicated capacitor!

This is a problem because of pcb place constraints.

Q: Are there any of these caps to avoid, if connection VDDIO pin to GNB or 3,3V layers are as short as possibe and a 100nf cap for each side of the IC is provided ?

Any design hints to reduce amount of analog components welcome !

  • Hello,

    That is correct. Each pin needs to have a cap. TI recommends a minimum of 100nF decoupling caps on all VDDIO supply pins as close to the pins as possible.

    Best Regards,
    Adam Dunhoft
  • Hi Adam,

    problem is board space and we try to minimize components.

    Would it be suffucient to bundle adjacent Vdd pins with a common capacitor:

    e.g. 3 x Vdd pins with 0.1uF each bundled with one 0.33uF ?

  • Hi DJ-NG,

    I have not seen this done before. Let me dig a little to see if there are any risks with this method.

    Best Regards,
    Adam Dunhoft
  • Is the customer pushing the performance of the analog or high-speed digital?

    Does the customer have to pass EMI/EMC tests?

    I think this is a question of how much the customer is concerned with noise/emi. As you move the decoupling capacitors further away from the pins, the high frequency voltage and current transients caused by internal device switching have to propagate further before being absorbed by the decoupling capacitors - this increases system noise. The system may also be more susceptible to noise as there is more trace length between the decoupling capacitor and the supply pin that could pick up noise.