I'm setting up a F2812 McBsp as a slave in multichannel mode, and trying to use the FIFO at the same time. [16 bit words @16.6Mhz, 92 word frames, external Frame Sync and clock.
I am seeing a very specific pattern of data loss that occurs on ~10% of the chips tested. When the FIFO is empty, I re-load it with a test pattern: The high 8 bits are a counter: {0,1,2,3...} The low 8 bits are the FIFO depth when it is loaded. We expect to see something like {0x00, 0x11, 0x22, 0x32, 0x43 ...} - The counter increases sequentially, and the FIFO depth also increases, except for an instance when the a word is shifted out of the FIFO into DXR. What we see is that on up to 50% of the frames, we get {0x00, 0x22, 0x32,0x43...}. The second item loaded is not transmitted. The fact that the FIFO depth increases by 2 indicates clearly that 2 items were loaded but only one came out. I know that the FIFO load is being completed well before this processor's time slice in the frame starts.
On the chips that exhibit the problem it is 100% repeatable, although the frequency of glitches varies from chip-to-chip, and has some temperature dependence. Other chips never exhibit the problem and work perfectly with the same code. I've tried changing baud rate, data delay, DXDelay, XFIG. with no effect. I've tried 8,16, and 32 bit words, and the glitch remains - the 2nd word loaded into the FIFO disapears, regardless of its size.
It really feels to me like this is a race condition on the chip - that sometimes the word staged in DXR is clobbered when the McBsp's channels first become active in a given frame. Is there a configuration error here, or is this a silicon issue?
My configuration code follows:
McbspaRegs.SPCR2.bit.XRST = 0; // reset the transmitter
McbspaRegs.SPCR2.bit.FRST = 0; // reset the frame sync generator
McbspaRegs.SPCR2.bit.GRST = 0; // reset the sample rate generator.
McbspaRegs.SPCR1.bit.RRST=0; // Receiver reset
McbspaRegs.MFFTX.bit.XRESET = 0; // FIFO reset
//Configure the transmiter per SPRU061B, section 3.2.1
// "Programming the McBspRegisters for Desired Transmitter Operation"
// Global behavior:
McbspaRegs.SPCR1.bit.DLB = 0; // disable loopback.
McbspaRegs.SPCR1.bit.CLKSTP=0; // stop clock mode
McbspaRegs.MCR2.bit.XMCM = 1; // Disable masked channels - transmit on selected channels
McbspaRegs.MCR2.bit.XMCME = 1; // enable 8 partition Mode
McbspaRegs.SPCR1.bit.ABIS = 0; // A-bis mode OFF
//Data behavior:
McbspaRegs.XCR2.bit.XPHASE = 0; // single phase message
McbspaRegs.XCR1.bit.XWDLEN1 = 2; // word length = 16 bits
McbspaRegs.XCR1.bit.XFRLEN1 = 91; // frame length = 92 words
McbspaRegs.XCR2.bit.XFIG = 1; // Illegal frame sync restarts the transfer
McbspaRegs.XCR2.bit.XCOMPAND = 0; // No companding, MSB first
McbspaRegs.XCR2.bit.XDATDLY = 1; // one bit data delay
McbspaRegs.SPCR1.bit.DXENA = 0; // DX delay enable off
McbspaRegs.SPCR2.bit.XINTM = 3; // Interrupt on Frame sync error
//External sync and clock
{
McbspaRegs.PCR1.bit.FSXM = 0; // External Frame Sync through FSXP pin
McbspaRegs.SRGR2.bit.FSGM = 0; // transmit FSG control
McbspaRegs.PCR1.bit.FSXP = 0; // FSXP is active high
McbspaRegs.SRGR2.bit.FPER = 0; // Frame Sync Period is don't care (externally generated)
McbspaRegs.SRGR1.bit.FWID = 0; // FSG = 1 CLKG period
McbspaRegs.PCR1.bit.CLKXM = 0; // Tranmitter clock is external clock input
McbspaRegs.PCR1.bit.SCLKME = 1; // SRG from CLKX pin
};
//Clock Behavior:
//default polarity
McbspaRegs.SRGR1.bit.CLKGDV = 2; // CLK = 50MHz/3
McbspaRegs.SRGR2.bit.GYSNC = 0; // Not sync clk to external Frame
McbspaRegs.SRGR2.bit.CLKSM = 1; // select sample rate generator clk input
McbspaRegs.PCR1.bit.CLKXP = 0; // Transmit data sampled on rising edge of CLK
McbspaRegs.XCERA.all = 0x0000; //18 words starting @20.
McbspaRegs.XCERB.all = 0xfff0;
McbspaRegs.XCERC.all = 0x003f;
McbspaRegs.XCERD.all = 0;
McbspaRegs.XCERE.all = 0;
McbspaRegs.XCERF.all = 0;
McbspaRegs.XCERG.all = 0;
McbspaRegs.XCERH.all = 0;
// Configure the FIFO:
McbspaRegs.MFFTX.bit.MFFENA = 1; // enable the FiFO
McbspaRegs.MFFTX.bit.IL = 0; // Interrupt on transmit FIFO empty.
McbspaRegs.SPCR2.bit.XRST = 1; // reset the transmitter
McbspaRegs.SPCR2.bit.GRST = 1; // reset the sample rate generator.
// enable Interrupt service:
PieCtrlRegs.PIEIER6.bit.INTx6 = 1; // McBSP MXINT
IER |= M_INT6;