Compiler/TMS320F28377D: CPU2 CANA interrupt setup

Tool/software: TI C/C++ Compiler

Hello,

CANA communication has been successfully setup for CPU2.  CPU1 setups up the appropriate GPIO pins, gives CPU2 control of these pins, then gives CPU2 control of both CAN buses (via CPUSEL8).

CPU2 will later setup the clocks, then cal CANInit(CANA_BASE) (from the TI example code C:\ti\controlSUITE\device_support\F2837xD\v210\F2837xD_examples_Cpu1\can_external_transmit).  

Later, CPU2 writes to CAN_CTL and CAN_GLB_INT_EN.  This appears to have no affect upon inspection in CSS debug registers view.  EALLOW has no affect here.  

Under what conditions can CPU2 write to CanaRegs???

Thanks!