TMS320F280200: ADC Offset issue

Hi Amit,

The ADC input is not high-impedance like an op-amp input.  Instead it behaves more like an R-C charging network.  We have a model of this in the datasheet: "Figure 6-20. ADC Input Impedance Model"

The goal is to charge Ch to within 1/4 LSBs during the allotted S+H window (S+H duration is controlled by the ACQPS field in the SOC configuration register along with the ADCCLK).  

An approximation of the time constant for the ADC input is tc = (Rs+Ron)*Ch + Rs*Cp.  

With Rs = 100k, Ch = 1.6pF, Cp = 5pF, Ron = 3.4k, then tc = 665ns

1/4 LSB settling at 12-bit resolution requires -ln(0.25*(1/4096)) = 9.7 time constants

So the required settling time with 100k source impedance is at least 9.7*665ns = 6.5us.  

This is much longer than you can configure the S+H duration, so the input impedance will need to be reduced.  

Overall, if you are having issues with ADC input settling you can do some combination of increasing the S+H window duration by increasing the ACQPS setting (being mindful not to use an illegal value, as specified by the register definition in the ADC UG) or by decreasing the external R and/or C on the pin.  You can also make the C on the pin very large so that all the charge into the ADC comes from the external capacitor (but then you need to limit the sample-rate to allow the external capacitor to adequately recover between samples).