How to setup two external interrupts inside of another external interrupt

HI TI,

I wanna setup two external interrupts(XINT1 and XINT2) inside of another external interrupt (XINT3), Will it work?

Is there any documents on how to setup like this?

Also I ran into a setup problem of XINT3,  somehow XINT3 ISR function is not triggered even through I applied signal into it.

XIN2_ISR and XINT1_ISR works fine, XINT3_ISR has exact same setup as XINT1 and XINT2, but it just doesn't work. I might have missed something. Please Help and take a look on my GPIO setup.

Here are my following setup, base on the ControlSuit ExternalInterrupts Example:

Hardware: F28055

interrupt void xint1WR_isr(void);
interrupt void xint2RD_isr(void);
interrupt void xint3CS_isr(void);

// ISR functions found within this file.
   EALLOW;	// This is needed to write to EALLOW protected registers
   PieVectTable.XINT1 = &xint1WR_isr;
   PieVectTable.XINT2 = &xint2RD_isr;
   PieVectTable.XINT3 = &xint3CS_isr;
   EDIS;   // This is needed to disable write to EALLOW protected registers

// Clear the counters
   Xint1WR_Count = 0; // Count XINT1 interrupts
   Xint2RD_Count = 0; // Count XINT2 interrupts
   Xint3CS_Count = 0; // Count XINT3 interrupts

// Enable XINT1,XINT2 and XINT3 in the PIE: Group 1,12 interrupt 4,5 & 1
// Enable INT1 which is connected to WAKEINT:
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;          // Enable the PIE block
   PieCtrlRegs.PIEIER1.bit.INTx4 = 1;          // Enable PIE Group 1 INT4
   PieCtrlRegs.PIEIER1.bit.INTx5 = 1;          // Enable PIE Group 1 INT5
   PieCtrlRegs.PIEIER12.bit.INTx1 = 1;         // Enable PIE Group 12 INT1
   IER |= M_INT1;                              // Enable CPU INT1
   EINT;                                       // Enable Global Interrupts

// GPIO8 is input XINT1,  GPIO9 is input XINT2,  GPIO10 is input XINT3
   EALLOW;
   GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0;         // GPIO8
   GpioCtrlRegs.GPADIR.bit.GPIO8 = 0;          // input
   GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0;        // Synch to SYSCLOUT

   GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0;         // GPIO9
   GpioCtrlRegs.GPADIR.bit.GPIO9 = 0;          // input
   GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0;        // Synch to SYSCLOUT

   GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0;         // GPIO10
   GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;          // input
   GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0;        // Synch to SYSCLOUT
   EDIS;

// GPIO8 is XINT1, GPIO9 is XINT2,  GPIO10 is XINT3
   EALLOW;
   GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 8;   // XINT1 is GPIO8
   GpioIntRegs.GPIOXINT2SEL.bit.GPIOSEL = 9;   // XINT2 is GPIO9
  // GpioIntRegs.GPIOXINT3SEL.bit.GPIOSEL = 10;  // XINT3 is GPIO10
   GpioIntRegs.GPIOXINT3SEL.all = 10;    // XINT3 connected to GPIO10
   EDIS;

// Configure XINT1, XINT2 and XINT3
   XIntruptRegs.XINT1CR.bit.POLARITY = 1;      // Rising edge interrupt
   XIntruptRegs.XINT2CR.bit.POLARITY = 1;      // Rising edge interrupt
   XIntruptRegs.XINT3CR.bit.POLARITY = 0;      // Falling edge interrupt

// Enable XINT1, XINT2 and XINT3
   XIntruptRegs.XINT1CR.bit.ENABLE = 1;        // Enable XINT1
   XIntruptRegs.XINT2CR.bit.ENABLE = 1;        // Enable XINT2
   XIntruptRegs.XINT3CR.bit.ENABLE = 1;        // Enable XINT3

interrupt void xint1WR_isr(void)
{

Xint1WR_Count++;

// Acknowledge this interrupt to get more from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}

interrupt void xint2RD_isr(void)
{

Xint2RD_Count++;
// Acknowledge this interrupt to get more from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}
interrupt void xint3CS_isr(void)
{

Xint3CS_Count++;
// Acknowledge this interrupt to get more from group 12
PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
}