Hello,
I am trying to use I2C on F28027 and have problems setting the master clock correctly.
I am using a CPU clock at 60Mhz, I2CPSC is set to 4 for a 12MHz I2C module clock, I2CCLKH=10 and I2CCLKL=11 so the total master clock divider should be (10+11+5+5)=31 (d=5 for I2CPSC > 1). The master clock I was expecting is 12MHz / 31 = 387KHz, however using a logic analyser I see 333KHz, which is 12MHz / 36 if this makes any sense.
I tried with a 10MHz module clock too, setting I2CPSC=5, and I2CCLKH=I2CCLKL=8, to get 10MHz/(8+8+5+5)=385KHz but still get around 330KHz output.
I am building on top of a MotorWare example running on the F28027 Launchpad, so CPU clock is set correctly and verified via PWM, SPI frequency etc. Also, if I assume the I2C clock division works as described in the datasheet and the CPU clock is at fault, the actual CPU clock would need to be 60MHz*(333KHz/387KHz)=51.6MHz which is not an available option as far as I know.
