TMS320F28022: IIC issue: First bit data setup time calculation

Benjamin,

The setup time should comply with the I2C spec if the module clock (after prescale divider) is between 7 and 12 MHz. Can you please tell me your CPU frequency and I2C prescale register value?

Thanks,

Hi Adam,
The SYSCLKOUT is 50Mhz, and the I2C Module clock configuration shown as below, at this configuration, the data setup time is 256ns;
I2caRegs.I2CPSC.all = 4;
I2caRegs.I2CCLKL = 10;
I2caRegs.I2CCLKH = 5;

Modify the configuration as below, the data setup time is 376ns;
I2caRegs.I2CPSC.all = 5;
I2caRegs.I2CCLKL = 9;
I2caRegs.I2CCLKH = 6;

and also, the F28022 is worked as slave.

Expect for your reply, thanks.

Best Regards
Benjamin

Either configuration should be fine. If you want a longer setup time, you can use the prescale value of 5, but I don't see any reason for it.

Hi Adam,
The question is how to calculate the first bit data setup time while the F28022 worked as slave, could you kindly help on this?

I'll ask the Design team. It might take a couple days to get an answer.

Adam,
Very appreciated for your kindly support, and expect for your reply.

Benjamin
Best Regards

According to the Design team, SDA is driven five I2C module clocks after SCL goes low. The module clock frequency is equal to SYSCLK divided by the prescaler.

Adam,
Very appreciate for your kindly support. This thread can be closed. thanks.

Best Regards
Benjamin