I am new to the TI line of tools and have been trying to start sending a block of characters from the main program and have the TXFFINT load or reload the the FIFO until the block is send and then disable the interrupt.
Currently I can send a 64 byte block but the transmission starts as soon as the EINT instruction is executed. What I need to be is sent up the SCI and then start transmission when I enable the SCI.
Between the PIE and the SCI I do not have the correct initialization sequence. The is my current code.
//###########################################################################
//
//! \addtogroup f2803x_example_list
//! <h1>SCI Digital Loop Back with Interrupts(scia_loopback_interrupts)</h1>
//!
//! This program uses the internal loop back test mode of the peripheral.
//! Other then boot mode pin configuration, no other hardware configuration
//! is required. Both interrupts and the SCI FIFOs are used.
//!
//! A stream of data is sent and then compared to the received stream.
//! The SCI-A sent data looks like this: \n
//! 00 01 \n
//! 01 02 \n
//! 02 03 \n
//! .... \n
//! FE FF \n
//! FF 00 \n
//! etc.. \n
//! The pattern is repeated forever.
//!
//! \b Watch \b Variables \n
//! - \b sdataA - Data being sent
//! - \b rdataA - Data received
//! - \b rdata_pointA - Keep track of where we are in the datastream.
//! This is used to check the incoming data
//
//###########################################################################
// $TI Release: F2803x C/C++ Header Files and Peripheral Examples V130 $
// $Release Date: May 8, 2015 $
// $Copyright: Copyright (C) 2009-2015 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#define CPU_FREQ 60E6
#define LSPCLK_FREQ CPU_FREQ/4
#define SCI_FREQ 115200// dtr 100E3
#define SCI_PRD (LSPCLK_FREQ/(SCI_FREQ*8))-1
// Prototype statements for functions found within this file.
__interrupt void sciaTxFifoIsr(void);
__interrupt void sciaRxFifoIsr(void);
__interrupt void scibTxFifoIsr(void);
__interrupt void scibRxFifoIsr(void);
void scia_fifo_init(void);
void scib_fifo_init(void);
void error(void);
void SDV2InitSysCtrl(void);
// Global variables
#define BUFFER_SIZE (64)
Uint16 sdataA[64]; // Send data for SCI-A
Uint16 rdataA[64]; // Received data for SCI-A
Uint16 x = 1;
void main(void)
{
Uint16 i;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2803x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the DSP2803x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio();
// Setup only the GP I/O only for SCI-A and SCI-B functionality
// This function is found in DSP2803x_Sci.c
InitSciaGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2803x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2803x_DefaultIsr.c.
// This function is found in DSP2803x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize all the Device Peripherals:
scia_fifo_init(); // Init SCI-A
// Step 5. User specific code, enable interrupts:
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER |= M_INT9; // Enable CPU INT
EINT;
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;);
}
void error(void)
{
__asm(" ESTOP0"); // Test failed!! Stop!
for (;;);
}
__interrupt void sciaTxFifoIsr(void)
{
Uint16 i;
static Uint16 sent = 0;
for(i=0; i< 2; i++)
{
SciaRegs.SCITXBUF=sdataA[ sent++ + i]; // Send data
}
if( sent < BUFFER_SIZE)
{
SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}
else
{
sent = 0;
for(i = 0; i <BUFFER_SIZE ; i++)
{
sdataA[i] = 0;
}
SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}
}
__interrupt void sciaRxFifoIsr(void)
{
Uint16 i, received = 0;
if( x == 1 )
{
x = 0;
return;
}
for(i=0;i<2;i++)
{
rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data]
}
if( received < BUFFER_SIZE)
{
received += 2;
}
else
{
received = 0;
}
SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
}
void scia_fifo_init()
{
SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;
SciaRegs.SCIHBAUD = 0x0000;
SciaRegs.SCILBAUD = SCI_PRD;
SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCIFFTX.all=0xC022;
SciaRegs.SCIFFRX.all=0x0022;
SciaRegs.SCIFFCT.all=0x00;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
}
//===========================================================================
// No more.
//===========================================================================
