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CCS/TMS320F28377D: CPU2 FLASH OTP Zx_BOOTMODE

Stephen Bialkowski
Intellectual 450 points
Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hello,

Our goal is to have both cores boot from FLASH upon power up without the emulator on a custom board.  Both appear to load and run when the emulator is connected.  I believe we need to write 0x00000B5A to CPU2's Zx_BOOTCTRL registers.  I have tried through both the CCS debug setup and by using the latest cmd and *_ZoneSelectBlock.asm files.  It appears as though these values are not written (by checking registers and 0x78x00 in memory during debug session).  

I have made note of of using the latest v210 2837xD_dcsm_lnk_cpu2.cmd file.  I have also tried using the dcsm cmd file from the newest CPU1 Blinky with dcsm example.  I see the registers make it into the resulting *.map file.  

What could be wrong here?

Thanks,

Stephen

  • 0
    TI__Guru** 115271 points
    Hi Stephen,

    To BOOT from Flash you don't have to program the BOOTCTRL location in OTP. Which document you are referring?

    Vivek Singh
  • 0 in reply to Vivek Singh
    Intellectual 450 points
    Vivek,
    Thanks for the quick reply. I have been referring to the TRM and various posts here.
    In this case, I have two concerns.
    1) Under what circumstances would CPU2 get to main() from FLASH with the emulator connected, and fail to get to main() when emulator isn't connected?
    2) I will need to know how to write to Zx_BOOTCTRL. Can you advise how to write to successfully Zx_BOOTCTRL?

    Thanks again.
    Stephen
  • 0 in reply to Stephen Bialkowski
    TI__Guru** 115271 points
    Hi Stephan,

    You can have the CPU1 boot CPU2 from FLASH via IPC command.
    Check this post - e2e.ti.com/.../462637

    About programming Zx_BOOTCTRL, you are trying correct method. You can program it via Flash plug-in or by including this in .out file. If it's not working then please make sure you have all the latest update in CCS. You can check for update by clicking Help -> Check for update in CCS.

    Regards,

    Vivek Singh
  • 0 in reply to Vivek Singh
    Intellectual 450 points

    Vivek,

    Thanks for getting back to me.  I experience the symptom in the referenced post.  I am using IPC to boot CPU2.  I later found the CPU2 build was missing startup code, and the watchdog was resetting CPU2.  But these weren't the only problems.  How it ever worked must have been some CCS voodoo.  I mean that in the best way possible.  

    The hard part here is it seems impossible to see what CPU2 is actually doing.  In an attempt to gain visibility into what CPU2 was doing, I would power up the device, then connect JTAG, then debug.  The problem then becomes the emulator will reset the CPUs when it connects.  I thought that I had setup a debug configuration to do nothing but connect to the already running binary (and not reset the cores).  It doesn't seem to work anymore.  So, either I confused myself, or I changed one of the settings that contributed to the magic combo.  Can you suggest a way to setup a debug configuration to do just this for CPU2 on the TMS320F28377D?  Or at least say whether it's possible?

    Also, I remember having issues updating in the past now that you mention it.  I have since trashed the 6.2 install, and installed 7.0.  Unfortunately, we needed working code several days ago.  So, I reverted and built for CPU1 only.  I will check when we have a need to go down that path again and try to remember to report back.  

    Stephen

  • 0 in reply to Stephen Bialkowski
    TI__Guru** 115271 points
    Stephen,

    To avoid reset on connect, you need to comment out "GEL_Reset(); /* Reset DSP */" function call inside "OnTargetConnect()" function in CPU2 Gel file. Is that what you tried?

    Vivek Singh
  • 0 in reply to Vivek Singh
    TI__Guru** 115271 points

    Stephen, I hope you were able to get this working. Let us know if you have any further queries on this.