TMS320C28346: Questions about XTIFG configuration

Uchida-san,

a."XRDACTIVE ≧ 6" is described in secction 4.1,4.2 and 4.3. 

　    It is described that AR means (XRDACTIVE+WS+1) x tc(xtim).

　    I think correct description when AR ≧ 6  is "XRDACTIVE ≧ 5" , isn't it ?

Your understanding is correct. This is known issue and has been registered in our system to fix in next release.

b."XWRACTIVE = 2, XWRACTIVE = 4, XWRTRAIL = 2" is descrribed in Figure 14.

　    I think correct description is "XWRLEAD = 2, XWRACTIVE = 4, XWRTRAIL = 2" , isn't it?

That is correct. This is a typo. I'll mention this as well to fix in next release.

2.If the answer of question 1-b is YES, why figure 14 is described when "XWRLEAD = 2" although section 4.1, 4.2, 4.3 specifies "XWRLEAD ≧ 3" ?

These timing diagrams are just for example and have been created to go in different devices documents and in some cases  " XWRLEAD ≧ 1" is valid. User need to use correct value based on device specific constraints.

3.Is my understanding correct that BCYC and BANK bit in the XBANK Register works as following flows?

I will get back to you later on this one.

Regards,

Vivek Singh

Hi Vivek,

Thank you for your reply.

I'm also waiting for your contact about question3.

Regards,

uchida-k

Hi Vivek,

Can I ask additional questions?

1. Which is write trail period invalid or 0 when XWRTRAIL = 00b ?

    Write Trail Period is blank when XWRTRAIL = 00b in the table 7 at the page of 27, SPRUFN4A.

2.Do you have something tools which detect setting invalid value to the resister ?

   For example, in case of setting XRDACTIVE = 0 although XRDACTIVE ≧ 6 according to section 4 in the SPRUFN4A.

3.If you have something advises about following question in the previous post, please let me know.

   -> Is my understanding correct that BCYC and BANK bit in the XBANK Register works as following flows? 

   

Regards,

uchida-k