CCS/LAUNCHXL-F28377S: HRPWM and Deadband Modul

//###########################################################################
//
// FILE:    HRPWM_PrdUpDown_SFO_V8.c
//
// TITLE:   F2837xS Device HRPWM SFO V8 High-Resolution Period (Up-Down Count)
//          example
//
//! \addtogroup cpu01_example_list
//! <h1> HRPWM SFO Test (hrpwm_prdupdown_sfo_v8)</h1>
//!
//! This program requires the F2837xS header files, which include
//! the following files required for this example:
//! SFO_V8.h and SFO_TI_Build_V8_FPU.lib
//!
//! Monitor ePWM1-ePWM8 A/B pins on an oscilloscope.
//! DESCRIPTION:
//!
//! This example modifies the MEP control registers to show edge displacement
//! for high-resolution period with ePWM in Up-Down count mode
//! due to the HRPWM control extension of the respective ePWM module.
//!
//! This example calls the following TI's MEP Scale Factor Optimizer (SFO)
//! software library V8 functions:
//!
//!
//! \b int \b SFO(); \n
//! updates MEP_ScaleFactor dynamically when HRPWM is in use
//! updates HRMSTEP register (exists only in EPwm1Regs register space)
//! with MEP_ScaleFactor value
//! - returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255
//!   (Auto-conversion may not function properly under this condition)
//! - returns 1 when complete for the specified channel
//! - returns 0 if not complete for the specified channel
//!
//!
//! This example is intended to explain the HRPWM capabilities. The code can be
//! optimized for code efficiency. Refer to TI's Digital power application
//! examples and TI Digital Power Supply software libraries for details.
//!
//! All ePWM1-8 A/B channels will have fine
//! edge movement due to the HRPWM logic
//!
//! =======================================================================
//! NOTE: For more information on using the SFO software library, see the
//! F2837xS High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
//! =======================================================================
//!
//! To load and run this example:
//! -# **!!IMPORTANT!!** - in SFO_V8.h, set PWM_CH to the max number of
//!    HRPWM channels plus one. For example, for the F2837xS, the
//!    maximum number of HRPWM channels is 8. 8+1=9, so set
//!    #define PWM_CH 9 in SFO_V8.h. (Default is 8)
//! -# Run this example at maximum SYSCLKOUT
//! -# Activate Real time mode
//! -# Run the code
//! -# Watch ePWM A / B channel waveforms on an Oscilloscope
//! -# In the watch window:
//!    Set the variable UpdateFine = 1  to observe the ePWMxA & ePWMxB output
//!    with HRPWM capabilities (default)
//!    Observe the period/frequency of the waveform changes in fine MEP steps
//! -# In the watch window:
//!    Change the variable UpdateFine to 0, to observe the
//!    ePWMxA & ePWMxB output without HRPWM capabilities
//!    Observe the period/frequency of the waveform changes in coarse SYSCLKOUT
//!    cycle steps.
//!
//
//###########################################################################
// $TI Release: F2837xS Support Library v200 $
// $Release Date: Tue Jun 21 13:52:16 CDT 2016 $
// $Copyright: Copyright (C) 2014-2016 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "SFO_V8.h"

//
// Defines
//
#define PWM_CH            9        // # of PWM channels
#define STATUS_SUCCESS    1
#define STATUS_FAIL       0

//
// Globals
//
float Dutycycle = 0.5;					// Tastgrad | theoretisch von 0-1 | bei uns 0.5
float PWM_Periodendauer =  100.25;   	// bezogen auf 10ns
Uint16 UpdateFine, PeriodFine, status;

int MEP_ScaleFactor; // Global variable used by the SFO library
                     // Result can be used for all HRPWM channels
                     // This variable is also copied to HRMSTEP
                     // register by SFO(0) function.

//
// Array of pointers to EPwm register structures:
// *ePWM[0] is defined as dummy value not used in the example
//
volatile struct EPWM_REGS *ePWM[PWM_CH] =
{  &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs,
   &EPwm6Regs, &EPwm7Regs, &EPwm8Regs};

//
// Function Prototypes
//
void HRPWM_Config(int);
void error(void);
void epwm2_isr(void);
void update_T_PWM(float);
//
// Main
//
void main(void)
{
    int i;

    EALLOW; // This is needed to write to EALLOW protected registers

//
// Initialize System Control for Control and Analog Subsystems
// Enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
//
    InitSysCtrl();

    EDIS;

//
// EPWM1A and EPWM1B through all PWMS
//
    InitEPwmGpio();

    DINT; // Disable CPU interrupts

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
//

//
// This function is found in the F2837xS_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    EALLOW;
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xS_DefaultIsr.c.
// This function is found in F2837xS_PieVect.c.
//
    InitPieVectTable();

    // epwm2_isr mit Interrupt 3.2 verkn�pfen
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.EPWM2_INT = &epwm2_isr;			// 3.2 - ePWM2 Interrupt
    EDIS;   // This is needed to disable write to EALLOW protected registers
    //


    //  F�r  Funktion epwm2_isr
    // Enable CPU INT3 which is connected to EPWM1-3 INT:
    IER |= M_INT3; // -> fuer epwm interrupt
    //

    // * F�er epwm2_isr
    PieCtrlRegs.PIEIER3.bit.INTx2 = 1;










//
// Initialize system variables, enable HRPWM
//
    UpdateFine = 1;
    PeriodFine = 0;
    status = SFO_INCOMPLETE;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;   // Enable Global interrupt INTM
    ERTM;   // Enable Global realtime interrupt DBGM

//
// Calling SFO() updates the HRMSTEP register with calibrated MEP_ScaleFactor.
// HRMSTEP must be populated with a scale factor value prior to enabling
// high resolution period control.
//
    while(status == SFO_INCOMPLETE) // Call until complete
    {
        status = SFO();
        if (status == SFO_ERROR)
        {
            error();    // SFO function returns 2 if an error occurs & # of MEP
        }               // steps/coarse step exceeds maximum of 255.
    }

//
// ePWM and HRPWM register initialization
//
    HRPWM_Config(1000);   // ePWMx target
    for(;;)
    {
        //
        // Sweep PeriodFine as a Q16 number from 0.2 - 0.999
        //
        for(PeriodFine = 0x3333; PeriodFine < 0xFFBF; PeriodFine++)
        {
            if(UpdateFine)
            {
                //
                // Because auto-conversion is enabled, the desired
                // fractional period must be written directly to the
                // TBPRDHR (or TBPRDHRM) register in Q16 format
                // (lower 8-bits are ignored)
                //
                // EPwm1Regs.TBPRDHR = PeriodFine;
                //
                // The hardware will automatically scale
                // the fractional period by the MEP_ScaleFactor
                // in the HRMSTEP register (which is updated
                // by the SFO calibration software).
                //
                // Hardware conversion:
                // MEP delay movement = ((TBPRDHR(15:0) >> 8) *  HRMSTEP(7:0) +
                //                       0x80) >> 8
                //
                for(i=1; i<PWM_CH; i++)
                {
                  //  (*ePWM[i]).TBPRDHR = 0x3333; //In Q16 format
                }
            }
            else
            {
                //
                // No high-resolution movement on TBPRDHR.
                //
                for(i=1; i<PWM_CH; i++)
                {
                  //  (*ePWM[i]).TBPRDHR = 0;
                }
            }

            //
            // Call the scale factor optimizer lib function SFO(0)
            // periodically to track for any change due to temp/voltage.
            // This function generates MEP_ScaleFactor by running the
            // MEP calibration module in the HRPWM logic. This scale
            // factor can be used for all HRPWM channels. HRMSTEP
            // register is automatically updated by the SFO function.
            //
//            status = SFO(); // in background, MEP calibration module
//                            // continuously updates MEP_ScaleFactor
//
//            if(status == SFO_ERROR)
//            {
//                error();   // SFO function returns 2 if an error occurs & # of
//            }              // MEP steps/coarse step exceeds maximum of 255.
        } // end PeriodFine for loop
    } // end infinite for loop
}

//
// HRPWM_Config - Configures all ePWM channels and sets up HRPWM
//                on ePWMxA channels &  ePWMxB channels
//
void HRPWM_Config(period)
{
    Uint16 j;

    //
    // ePWM channel register configuration with HRPWM
    // ePWMxA toggle low/high with MEP control on Rising edge
    //
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;   // Disable TBCLK within the EPWM
    EDIS;

//    for(j=1; j<PWM_CH; j++)
//    {
        EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;  // set Shadow load
        EPwm2Regs.TBPRD = period;               // PWM frequency = 1/(2*TBPRD)
        EPwm2Regs.CMPA.bit.CMPA = period / 2;   // set duty 50% initially
        EPwm2Regs.CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
        EPwm2Regs.CMPB.bit.CMPB = period / 2;   // set duty 50% initially
        EPwm2Regs.CMPB.bit.CMPBHR = (1 << 8);   // initialize HRPWM extension
        EPwm2Regs.CMPB.all |= 1;
        EPwm2Regs.TBPHS.all = 0;
        EPwm2Regs.TBCTR = 0;

        EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
                                                        // count mode
        EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
        EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
        EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;          // TBCLK = SYSCLKOUT
        EPwm2Regs.TBCTL.bit.FREE_SOFT = 11;

       // EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // LOAD CMPA on CTR = 0
       // EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
        EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;  // LOAD CMPA on CTR = 0
        EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
        EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
        EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

        EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;             // PWM toggle high/low
        EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
        EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;             // PWM toggle high/low
        EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR;

        EALLOW;
        EPwm2Regs.HRCNFG.all = 0x0;
        EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP;          // MEP control on
                                                         // both edges.
        EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;          // CMPAHR and TBPRDHR
                                                         // HR control.
        EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;  // load on CTR = 0
                                                         // and CTR = TBPRD
        EPwm2Regs.HRCNFG.bit.EDGMODEB = HR_BEP;         // MEP control on
                                                         // both edges
        EPwm2Regs.HRCNFG.bit.CTLMODEB = HR_CMP;         // CMPBHR and TBPRDHR
                                                         // HR control
        EPwm2Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
                                                         // and CTR = TBPRD
        EPwm2Regs.HRCNFG.bit.AUTOCONV = 1;        // Enable autoconversion for
                                                   // HR period

        EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1;    // Enable TBPHSHR sync
                                                   // (required for updwn
                                                   //  count HR control)
        EPwm2Regs.HRPCTL.bit.HRPE = 1;            // Turn on high-resolution
                                                   // period control.

        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;      // Enable TBCLK within
                                                   // the EPWM
        EPwm2Regs.TBCTL.bit.SWFSYNC = 1;          // Synchronize high
                                                   // resolution phase to
                                                   // start HR period
        EDIS;
//    }





    // ohne EPwm2Regs.DBCTL.bit.POLSEL EPwm2Regs.DBRED EPwm2Regs.DBFED PWM2A = PWM2B
    // Setzen der Totzeit
    // Active Low complementary PWMs - setup the deadband | Figure 13-33 Technical reference manual
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // rising edge delay and falling edge delay enabled
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;      // Polarity select Control EPWMxB is inverted || 10: Active high complementary (AHC). EPWMxB is inverted.
    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;         // Dead-Band Input Mode Control: EPWMxA is source for rising and falling edge
    EPwm2Regs.DBRED.all = 10;                    // rising edge delay value
    EPwm2Regs.DBFED.all = 10;                    // falling edge delay value


    // test shadow deadband

//    EPwm2Regs.DBCTL.bit.LOADFEDMODE = 2;
//    EPwm2Regs.DBCTL.bit.LOADREDMODE = 2;
//    EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 1;
//    EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 1;

   // EPwm2Regs.DBCTL2.bit.SHDWDBCTLMODE = 1;
   // EPwm2Regs.DBCTL2.bit.LOADDBCTLMODE = 1;


    // Interrupt where we will change the Compare Values epwm2_isr
    //EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;  // Select INT on Zero event
    	   	   	   	// Enable event time-base counter equal to zero. TBCTR = 0x00
    EPwm2Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPB;
    EPwm2Regs.ETSEL.bit.INTEN = 1;                  // Enable INT
	// These bits determine how many selected ETSEL[INTSEL] events
	//  need to occur before an interrupt is generated
    EPwm2Regs.ETPS.bit.INTPRD = ET_1ST;             // Generate INT on 1st event


}

//
// error - Halt debugger when error occurs
//
void error (void)
{
    ESTOP0;         // Stop here and handle error
}
//************************interrupt PWM*********************************
__interrupt void epwm2_isr(void)
//interrupt void adca1_isr(void)
{

	EPwm2Regs.ETSEL.bit.INTEN = 0;
	GpioDataRegs.GPASET.bit.GPIO12 = 1;

	//while(AdcbRegs.ADCCTL1.bit.ADCBSY);

	EPwm2Regs.ETSEL.bit.SOCAEN = 0;  //disable SOCA um nicht permanent neuen abtastwert zu generieren

	// Hochsetzen des GPIO Pins um zu wissen wann man in der Interrupt Funktion ist
	//GpioDataRegs.GPASET.bit.GPIO12 = 1;  // Load output latch


	//EPwm2Regs.TBPRDHR = 0x3333;
    // rufe update_compare  auf
	//update_T_PWM(PWM_Periodendauer);
    // Clear INT flag for this timer




	//EPwm2Regs.TBPRD = 999;
	EPwm2Regs.TBPRDHR = 0x3333;

    //EPwm2Regs.CMPA.bit.CMPA = 500;
    //EPwm2Regs.CMPA.bit.CMPAHR = 0x3333;






	EPwm2Regs.ETCLR.bit.INT = 1; // zur�cksetzten n�tig da sonst kein weiterer interrupt erzeugt werden kann

    // Acknowledge this interrupt to receive more interrupts from group 3
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;



    // Clearen des GPIO Pins damit man wei� wann der Interrupt fertig ist
    //GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;  // Writing a 1 will force GPIO0 output data latch to 0
    EPwm2Regs.ETSEL.bit.SOCAEN = 1;  //enable SOC on A Group

	//GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;  // Writing a 1 will force GPIO0 output data latch to 0
	EPwm2Regs.ETSEL.bit.INTEN = 1;

}

void update_T_PWM(float PWM_T) //
{
	// lokale Variablen

	float temp; // -1 wichtig weil 999 im TBPRD Register 100kHz entsprechen
	temp = PWM_T - 1;
	Uint16 TBPRD_reg_val, TBPRDHR_reg_val; 	// Register Werte fuer TBPRD, TBPRDHR
	Uint16 CMPA_reg_val, CMPAHR_reg_val;
	long temp_1;




	// Setzen der PWM_Periodendauer
	TBPRD_reg_val = (unsigned int)temp; 	// grober Wert -1 weil 999 100kHz entspricht bei up mode leichter fuer user
	temp = temp - TBPRD_reg_val;			// (grober+feiner) Wert - grober Wert = feiner Wert in double dezimal
	temp = temp*65536;						// double auf Register Gr��e bezogen
	TBPRDHR_reg_val = (unsigned int)temp; 	// feiner Wert auf Registergr��e bezogen

	EPwm2Regs.TBPRD = TBPRD_reg_val;
	EPwm2Regs.TBPRDHR = TBPRDHR_reg_val;






	// Anpassen des PWM Duty Cycle zur neuen Periodendauer
	temp = ((EPwm2Regs.TBPRD*Dutycycle) - (unsigned int)(EPwm2Regs.TBPRD*Dutycycle));
	temp_1 = temp*65536 + Dutycycle*EPwm2Regs.TBPRDHR; // beide Nachkommastellen zusammen
    if ((temp_1) >= 65536)
    {
    	CMPA_reg_val = (unsigned int)(Dutycycle*EPwm2Regs.TBPRD + 1);
    	CMPAHR_reg_val = (unsigned int)(temp_1-65536);
    }
    else
    {
    	CMPA_reg_val = (unsigned int)(Dutycycle*EPwm2Regs.TBPRD);
    	CMPAHR_reg_val = (unsigned int)(temp_1);
    }



    EPwm2Regs.CMPA.bit.CMPA = CMPA_reg_val;
    EPwm2Regs.CMPA.bit.CMPAHR = CMPAHR_reg_val;


   return;
}







//
// End of file
//