Other Parts Discussed in Thread: CONTROLSUITE
Hi,
I am trying to debug an application for the F28377D, including code to run on the CLA. It all used to work fine a few weeks ago but I had to migrate my project to Mac OS and I am now mapping some of the F28377D code to Flash.
My issue: I cannot seem to load properly the CLA program. When I attempt to load symbols the debugger point to 0x00000000. I checked the .map file and it seems that the Cla1Prog code is in Flash and is properly copied to RAM. I really have no clue how to fix this. Any idea?
Here's my .cmd file:
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x200;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMGS2 : origin = 0x00E000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0_1 : origin = 0x00C000, length = 0x002000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}
SECTIONS
{
ramfuncs : > RAMM0 PAGE = 0
.cinit : > FLASHA PAGE = 0, ALIGN(4)
.pinit : > FLASHA PAGE = 0, ALIGN(4)
.text : > FLASHB PAGE = 0, ALIGN(4)
codestart : > BEGIN, PAGE = 0
.stack : > RAMM1, PAGE = 1
.ebss : > RAMGS0_1, PAGE = 1 /* >>LS1 LS2*/
.esysmem : > RAMGS0_1, PAGE = 1 /* LS2 */
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
/* Initalized sections go in Flash */
.econst : > FLASHC, PAGE = 0, ALIGN(4)
.switch : > FLASHC PAGE = 0, ALIGN(4)
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
/* CLA specific sections */
/* CLA specific sections */
Cla1Prog : LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4)
CLADataLS1 : > RAMLS1, PAGE=1 /* Remove LS1 and LS2 from these sections */
CLADataLS2 : > RAMLS2, PAGE=1
CLADataLS3 : > RAMLS3, PAGE=1
CLADataLS4 : > RAMLS4, PAGE=1
CLADataLS5 : > RAMLS5, PAGE=1
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
/* The following section definition are for SDFM examples */
AcquisitionChannels : > RAMGS14, PAGE = 1, fill=0x0000
ExcitationChannels : > RAMGS14, PAGE = 1, fill=0x0000
Cpu1ToCpu2ProcessingInfo : > RAMGS14, PAGE = 1, fill=0x0000
BLETransmissionBuffer : > RAMGS4, PAGE = 1, fill=0x0000
LockInBuffersIn1A : > RAMGS5 PAGE = 1, fill=0x0000
LockInBuffersIn1B : > RAMGS6 PAGE = 1, fill=0x0000
LockInBuffersIn2A : > RAMGS7, PAGE = 1, fill=0x0000
LockInBuffersIn2B : > RAMGS8, PAGE = 1, fill=0x0000
Cpu2ToCpu1ProcessingInfo : > RAMGS8, PAGE = 1, fill=0x0000
Cpu2ToCpu1ProcessingInfo2 : > RAMGS8, PAGE = 1, fill=0x0000
Cpu2ToCpu1FilteringInfo : > RAMGS8, PAGE = 1, fill=0x0000
LockInBuffersOutI : > RAMGS9, PAGE = 1, fill=0x0000
LockInBuffersOutQ : > RAMGS10, PAGE = 1, fill=0x0000
LUTs : > RAMGS11, PAGE = 1, fill=0x0000
FIRFilters : > RAMGS11, PAGE = 1, fill=0x0000
FilteringProcBuffer : > RAMGS12, PAGE = 1, fill=0x0000
FilteringOutputBuffers : > RAMGS13, PAGE = 1, fill=0x0000
/* CPU to CPU message rams sections*/
Cpu2ToCpu1Msg : > CPU2TOCPU1RAM, PAGE = 1
Cpu1ToCpu2Msg : > CPU1TOCPU2RAM, PAGE = 1
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
GROUP
{
.TI.ramfunc
{ -l F021_API_F2837xD_FPU32.lib}
} LOAD = FLASHE,
RUN = RAMGS2,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
#else
GROUP
{
ramfuncs
{ -l F021_API_F2837xD_FPU32.lib}
} LOAD = FLASHE,
RUN = RAMGS2,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
#endif
#endif
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS4, PAGE = 1
.scratchpad : > RAMLS4, PAGE = 1
.bss_cla : > RAMLS4, PAGE = 1
.const_cla : LOAD = FLASHC
RUN = RAMLS4,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 1
#endif //CLA_C
}
Thanks for your help!
Best regards,
