Hi sir,
I am working on bldc motor control application. I am using TMS320f2808 dsp controller for this application.
The working code is migrated from 2407 to 2808, to control bldc motor six pwm pulses is required.
From hall sensor, 3 signals are obtained , according to that sequence pwm pulses are generated.
pwm pulses are named as shown below
Epwm1A -> R(top), Epwm1B-> R(bottom) Epwm2A -> Y(top), Epwm2A -> Y(bottom), Epwm3A -> B(top) Epwm3B -> B(bottom)
Hall sensor sequence
A B C PWM PATTERN
o o 1 Y(top) & R(bottom)
o 1 1 Y(top) & B(bottom)
0 1 0 R(top) & B(bottom)
1 1 0 R(top) & Y(bottom)
1 0 0 B(top) & Y(bottom)
1 0 1 B(top) & R(bottom)
To obtain the above pwm pattern, I am using the following action settings are made
case 1.(0 0 1):
EPwm1Regs.AQCSFRC.bit.CSFA = 2;
EPwm1Regs.AQCSFRC.bit.CSFB = 0;
EPwm2Regs.AQCSFRC.bit.CSFA = 0;
EPwm2Regs.AQCSFRC.bit.CSFB = 2;
EPwm3Regs.AQCSFRC.bit.CSFB = 2;
EPwm3Regs.AQCSFRC.bit.CSFA = 2;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm1Regs.CMPA.half.CMPA=EPwm1Regs.CMPB=((pwm_by_4) - Duty_cycle);
EPwm2Regs.CMPA.half.CMPA=EPwm2Regs.CMPB=((pwm_by_4) + Duty_cycle);
case 2. (0 1 1):
EPwm1Regs.AQCSFRC.bit.CSFA = 2;
EPwm1Regs.AQCSFRC.bit.CSFB = 2;
EPwm2Regs.AQCSFRC.bit.CSFA = 0;
EPwm2Regs.AQCSFRC.bit.CSFB = 2;
EPwm3Regs.AQCSFRC.bit.CSFA = 2;
EPwm3Regs.AQCSFRC.bit.CSFB = 0;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET;
EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm2Regs.CMPA.half.CMPA=EPwm2Regs.CMPB=((pwm_by_4) + Duty_cycle);
EPwm3Regs.CMPA.half.CMPA=EPwm3Regs.CMPB=((pwm_by_4) - Duty_cycle);
In case1, Y(top) & R(bottom) pulses are released and all other pulses are forced to high,
similarly in case2 , Y(top) & B(bottom) pulses are released and all other pulses are forced to high,
The problem is when there is change from R(bottom) to B(bottom), there is a delay b/w them, this delay problem
is faced whenever there is a change in respective bottom pulses in all sequences but there is no delay when top pulses is changed
Because of this problem the current wave form is improper in bldc motor.
fig below are top pulse of one of the sequence
if we observe the pulse pattern when there is a switching occurs b/w two top pulses there is no delay.
fig below are bottom pulse of the same sequence
if we observe the pulse pattern when there is a switching occurs b/w two bottom pulses are get delayed exactly half of the pwm_by_4.
Due to this delay, when we observe in current waveform in the negative region , there is a sudden dip nearly zero current at the negative peak
Similarly when i reverse the action qualifier set & clear bit , the problem is observed in the top pulses.
fig below current waveform obtained when there is a delay in top pulses
if we observe the positive cycle and negative cycle, there is a sudden dip nearly zero in the mid of the positive cycle due to the delay problem in top pulse
similarly, there is a sudden dip nearly zero in the mid of the negative cycle when there is a delay in bottom pulse
the compare value is loaded to shadow register at zero or period, duty_cycle is 90% of pwm_by_4.This problem is not occurred when i use TMS320f2407 dsp with same code and same drive & motor
Please kindly help me to solve this problem
Thanks & Regards
Madhu Sagar M D
