LAUNCHXL-F28027F: I2C Slave Communication

I am trying to communicate to a Raspberry Pi via i2c with my 28027 acting as a slave-receiver in CCS 7. When I finally test that it is working with

// wait for bus to be busy test

while( I2caRegs.I2CSTR.bit.BB != 1 );

the while loop never exits. I am using the Raspberry Pi utility i2cdetect to 'ping' all addresses on the i2c bus and I can see that it is actually doing this with a digital scope.

 I have tried running the below software in RAM and Flash, each with no errors. In the function i2c_init() I make all the configurations to the i2ca registers but while in the debugger all the i2ca registers are 0x0000'd out as if the debugger cannot read them or they are never being modified in the first place.

System: Ubuntu 16.10

CCS Version: 7.0.0.00043

#include "f2802x_headers/include/F2802x_Device.h"
#include "f2802x_common/include/f2802x_examples.h"

#include "f2802x_common/include/clk.h"
#include "f2802x_common/include/cpu.h"
#include "f2802x_common/include/pie.h"
#include "f2802x_common/include/pll.h"
#include "f2802x_common/include/wdog.h"
#include "f2802x_common/include/gpio.h"
#include "f2802x_common/include/i2c.h"

CPU_Handle myCpu;
CLK_Handle myClk;
PIE_Handle myPie;
PLL_Handle myPll;
WDOG_Handle myWDog;
GPIO_Handle myGpio;

void setup_handles() {
    myClk = CLK_init((void *) CLK_BASE_ADDR, sizeof(CLK_Obj));
    myCpu = CPU_init((void *) NULL, sizeof(CPU_Obj));
    myPie = PIE_init((void *) PIE_BASE_ADDR, sizeof(PIE_Obj));
    myPll = PLL_init((void *) PLL_BASE_ADDR, sizeof(PLL_Obj));
    myWDog = WDOG_init((void *) WDOG_BASE_ADDR, sizeof(WDOG_Obj));
    myGpio = GPIO_init((void *) GPIO_BASE_ADDR, sizeof(GPIO_Obj));
}

void init_system() {
    // running from flash - copy RAM based functions to RAM
    #ifdef _FLASH
    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
    #endif

    // disable watchdog
    WDOG_disable(myWDog);

    // load factory calibration
    CLK_enableAdcClock(myClk);
    (*Device_cal )();
    CLK_disableAdcClock(myClk);

    // select the internal oscillator 1 (10 MHz) as the clock source
    CLK_setOscSrc(myClk, CLK_OscSrc_Internal);

    // setup the PLL for 10 MHz * 12 / 2 = 60 MHz
    PLL_setup(myPll, PLL_Multiplier_12, PLL_DivideSelect_ClkIn_by_2);

    // disable PIE and all interrupts
    PIE_disable(myPie);
    PIE_disableAllInts(myPie);
    CPU_disableGlobalInts(myCpu);
    CPU_clearIntFlags(myCpu);
}

void main() {
    setup_handles();
    init_system();

    GPIO_setPullUp(myGpio, GPIO_Number_32, GPIO_PullUp_Enable);
    GPIO_setPullUp(myGpio, GPIO_Number_33, GPIO_PullUp_Enable);

    GPIO_setQualification(myGpio, GPIO_Number_32, GPIO_Qual_ASync);
    GPIO_setQualification(myGpio, GPIO_Number_33, GPIO_Qual_ASync);

    GPIO_setMode(myGpio, GPIO_Number_32, GPIO_32_Mode_SDAA);
    GPIO_setMode(myGpio, GPIO_Number_33, GPIO_33_Mode_SCLA);

    CLK_enableSciaClock(myClk);

    i2c_init();

    // wait for bus to be busy test
    while( I2caRegs.I2CSTR.bit.BB != 1 );

    // wait for own slave on bus
    //while( I2caRegs.I2CSTR.bit.AAS != 1 );



    while (1)
        ;
}

void i2c_init(void){

    // i2c reset mode for configuration
    I2caRegs.I2CMDR.bit.IRS = 0;

    // module clock pre-scaler
    I2caRegs.I2CPSC.all = 5; // 60MHz / ( {5} + 1 ) = 10MHz (i2c requires 7 - 12 MHz)

    // master clock
    I2caRegs.I2CCLKL = 120;
    I2caRegs.I2CCLKH = 120;

    // take i2c out of reset
    I2caRegs.I2CMDR.bit.IRS = 1;


    // ==== I2C Mode Register (I2CMDR) ====

    // NACK mode
    // only taken into account when receiver
    I2caRegs.I2CMDR.bit.NACKMOD = 0;

    // FREE data mode
    I2caRegs.I2CMDR.bit.FREE = 1; // 1 required for slave mode

    // START (STT) condition bit mode
    // only taken into account when master
    I2caRegs.I2CMDR.bit.STT = 0;

    // STOP (STP) condition bit mode
    // only taken into account when master
    I2caRegs.I2CMDR.bit.STP = 0;

    // Master (MST) mode bit
    I2caRegs.I2CMDR.bit.MST = 0; // 0 for slave

    // Transmitter (TRX) mode bit
    I2caRegs.I2CMDR.bit.TRX = 0; // 0 for receiver

    // Expanded address bit (7 or 10-bit)
    I2caRegs.I2CMDR.bit.XA = 0; // 0 for normal 7-bit address

    // Repeat mode (RM) bit
    // only taken into account when master-transmitter
    I2caRegs.I2CMDR.bit.RM = 0;

    // Digital loopback (DLB) mode bit
    I2caRegs.I2CMDR.bit.DLB = 0;

    // I2C module reset bit
    // used to default all I2CSTR bits
    // required when configuring clock prescale and hold times
    // *may reset I2CMDR register?

    // Standard byte mode (STB)
    // only taken into account when master
    I2caRegs.I2CMDR.bit.STB = 0;

    // Free data format (FDF) bit
    I2caRegs.I2CMDR.bit.FDF = 0; // 0 for 7/10-bit addressing format

    // Bit count bits
    I2caRegs.I2CMDR.bit.BC = 000; // 8 bits per byte

    // ==== end of I2CMDR ====


    // own address
    I2caRegs.I2COAR = 0x0048;

    // read 1 byte
    I2caRegs.I2CCNT = 1;

}