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TMS320F28375D: ADC Reference Design Questions

Stuart Baker
Genius 10730 points

Part Number: TMS320F28375D

I have found the following two E2E threads with useful information, but I have a few followup questions for additional detail:

  1. What is the peak current consumption for VREFHI pin under worst case condition? What is the worst case condition for VREFHI pin?  This is assumed to be during conversion.
  2. There are four groups of ADC. Each group has its own VREFHI. Can they be internally connected together?  I think the answer is no, please confirm.
  3. Any layout guidance for BGA package because the requirement is :

“ Place at least a 1-µF capacitor on this pin for the 12-bit mode, ….. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins.”

Because all the pins are underneath the DSP, should the capacitor be placed on the opposite side of DSP and close to pins if double side component placement is used?  Is it valid to use a single sided component placement and still have the capacitor close enough to the VREF pins?

Thanks,

Stuart

  • 0
    TI__Guru 60865 points

    Hi Stuart,

    The average current consumption is specified in the datasheet. This is assuming the ADC in continuously converting at maximum speed.  The average current should scale with sample rate. 

    As far as the peak current, this is approximately 3mA for 12-bit mode and 15ma for 16-bit mode.  This would be for a small fraction of an ADCCLK during the conversion phase.  Most of this should be absorbed by the external capacitor.  

    The VREFHI pins are not connected internally.  

    You should be able to do single-sided component placement, as this will result in a similar distance to the die as the QFP packages.  Just get the caps as close as possible and make sure you have good ground planes.     

  • 0
    TI__Guru 62975 points
    Stuart,

    Each enabled Buffered DAC can also contribute 170 kΩ of load to VREFHI (roughly 20uA).

    -Tommy