• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 81 subscribers
  • Views 908 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28035: GENERATING 50 HZ FREQUENCY WITH VARYING DUTY CYCLE

MOHIT SHARMA18
Prodigy 30 points
Part Number: TMS320F28035
Other Parts Discussed in Thread: CONTROLSUITE

I want to generate 50 Hz varying duty cycle PWM with an ePwm block on Microcontroller TMS320F28035.But I am not able to get such low frequency.Here is my code for ePwm.When I  displaying on an oscilloscope I am also not able to get 50 % duty Cycle. This is for generating complementary pulses.

void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBPRD = 6000000; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

// Set Compare values
EPwm1Regs.CMPA.half.CMPA = 36000000; // Set compare A value
EPwm1Regs.CMPB = 3600000; // Set Compare B value

// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;

// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM1B on event B, downg count

}

  • 0
    TI__Guru 57255 points

    Hi Mohit,

    A few notes:
    1) The F28035 device's SYSCLK is, by default, configured to be 60MHz in many of the controlSUITE examples.
    2) According to the ePWM User Guide, TBPRD is only 16bits.  This means that values > than 65536 will wraparound (for example, 6000000 will get written to the register as 36224 - and this can be confirmed by setting by watching the EPwm1Regs.TBPRD register in the watch window after that line of code occurs).
    http://www.ti.com/lit/spruge9
    3) Therefore, if not using TBCTL[CLKDIV] or TBCTL[HSPCLKDIV] (keeping them as 1: not prescaling), the slowest PWM frequency that can be output is 60MHz/65536 = ~915Hz in count-up mode.  If using up-down-count mode, as you are, the rate is ~458Hz.
    4) In your code, you are using the prescalers.  This will make the slow down the PWM clock by 4*4, at the expense of also reducing resolution.  This will make the slowest PWM frequency that can be output as ~28.6Hz.

    By keeping your TBCTL[CLKDIV] and TBCTL[HSPCLKDIV] as they are, you should be able to output an ~50Hz PWM signal by setting TBPRD correctly.

    Hopefully this helps!


    Thank you,
    Brett